SLAS748F March   2011  – August 2015 DAC3482


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - Digital Specifications
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  Electrical Characteristics - Phase-Locked Loop Specifications
    9. 6.9  Timing Requirements - Digital Specifications
    10. 6.10 Switching Characteristics - AC Specifications
    11. 6.11 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Serial Interface
      2. 7.3.2  Data Interface
        1. Word-Wide Format
        2. Byte-Wide Format
      3. 7.3.3  Input FIFO
      4. 7.3.4  FIFO Modes of Operation
        1. Dual Sync Source Mode
        2. Single Sync Source Mode
        3. Bypass Mode
      5. 7.3.5  Clocking Modes
        1. PLL Bypass Mode
        2. PLL Mode
      6. 7.3.6  FIR Filters
      7. 7.3.7  Complex Signal Mixer
        1. Full Complex Mixer
        2. Coarse Complex Mixer
        3. Mixer Gain
        4. Real Channel Upconversion
      8. 7.3.8  Quadrature Modulation Correction (QMC)
        1. Gain and Phase Correction
        2. Offset Correction
        3. Group Delay Correction
      9. 7.3.9  Temperature Sensor
      10. 7.3.10 Data Pattern Checker
      11. 7.3.11 Parity Check Test
        1. Word-by-Word Parity
        2. Block Parity
      12. 7.3.12 DAC3482 Alarm Monitoring
      13. 7.3.13 LVPECL Inputs
      14. 7.3.14 LVDS Inputs
      15. 7.3.15 Unused LVDS Port Termination
      16. 7.3.16 CMOS Digital Inputs
      17. 7.3.17 Reference Operation
      18. 7.3.18 DAC Transfer Function
      19. 7.3.19 Analog Current Outputs
    4. 7.4 Device Functional Modes
      1. 7.4.1 Multi-Device Synchronization
        1. Multi-Device Synchronization: PLL Bypassed with Dual Sync Sources Mode
        2. Multi-Device Synchronization: PLL Enabled with Dual Sync Sources Mode
        3. Multi-Device Operation: Single Sync Source Mode
    5. 7.5 Programming
      1. 7.5.1 Power-Up Sequence
      2. 7.5.2 Example Start-Up Routine
        1. Device Configuration
        2. PLL Configuration
        3. NCO Configuration
        4. Example Start-Up Sequence
    6. 7.6 Register Map
      1. 7.6.1 Register Descriptions
        1.  Register Name: config0 - Address: 0x00, Default: 0x049C
        2.  Register Name: config1 - Address: 0x01, Default: 0x050E
        3.  Register Name: config2 - Address: 0x02, Default: 0x7000
        4.  Register Name: config3 - Address: 0x03, Default: 0xF000
        5.  Register Name: config4 - Address: 0x04, Default: No RESET Value (WRITE TO CLEAR)
        6.  Register Name: config5 - Address: 0x05, Default: Setup and Power-Up Conditions Dependent (WRITE TO CLEAR)
        7.  Register Name: config6 - Address: 0x06, Default: No RESET Value (READ ONLY)
        8.  Register Name: config7 - Address: 0x07, Default: 0xFFFF
        9.  Register Name: config8 - Address: 0x08, Default: 0x0000 (CAUSES AUTO-SYNC)
        10. Register Name: config9 - Address: 0x09, Default: 0x8000
        11. Register Name: config10 - Address: 0x0A, Default: 0x0000
        12. Register Name: config11 - Address: 0x0B, Default: 0x0000
        13. Register Name: config12 - Address: 0x0C, Default: 0x0400
        14. Register Name: config13 - Address: 0x0D, Default: 0x0400
        15. Register Name: config14 - Address: 0x0E, Default: 0x0400
        16. Register Name: config15 - Address: 0x0F, Default: 0x0400
        17. Register Name: config16 - Address: 0x10, Default: 0x0000 (CAUSES AUTO-SYNC)
        18. Register Name: config17 - Address: 0x11, Default: 0x0000
        19. Register Name: config18 - Address: 0x12, Default: 0x0000 (CAUSES AUTO-SYNC)
        20. Register Name: config19 - Address: 0x13, Default: 0x0000
        21. Register Name: config20 - Address: 0x14, Default: 0x0000
        22. Register Name: config21 - Address: 0x15, Default: 0x0000
        23. Register name: config22 - Address: 0x16, Default: 0x0000
        24. Register Name: config23 - Address: 0x17, Default: 0x0000
        25. Register Name: config24 - Address: 0x18, Default: NA
        26. Register Name: config25 - Address: 0x19, Default: 0x0440
        27. Register Name: config26 - Address: 0x1A, Default: 0x0020
        28. Register Name: config27 - Address: 0x1B, Default: 0x0000
        29. Register Name: config28 - Address: 0x1C, Default: 0x0000
        30. Register Name: config29 - Address: 0x1D, Default: 0x0000
        31. Register Name: config30 - Address: 0x1E, Default: 0x1111
        32. Register Name: config31 - Address: 0x1F, Default: 0x1140
        33. Register Name: config32 - Address: 0x20, Default: 0x2400
        34. Register Name: config33 - Address: 0x21, Default: 0x0000
        35. Register Name: config34 - Address: 0x22, Default: 0x1B1B
        36. Register Name: config35 - Address: 0x23, Default: 0xFFFF
        37. Register Name: config36 - Address: 0x24, Default: 0x0000
        38. Register Name: config37 - Address: 0x25, Default: 0x7A7A
        39. Register Name: config38 - Address: 0x26, Default: 0xB6B6
        40. Register Name: config39 - Address: 0x27, Default: 0xEAEA
        41. Register Name: config40 - Address: 0x28, Default: 0x4545
        42. Register Name: config41 - Address: 0x29, Default: 0x1A1A
        43. Register Name: config42 - Address: 0x2A, Default: 0x1616
        44. Register Name: config43 - Address: 0x2B, Default: 0xAAAA
        45. Register Name: config44 - Address: 0x2C, Default: 0xC6C6
        46. Register Name: config45 - Address: 0x2D, Default: 0x0004
        47. Register Name: config46 - Address: 0x2E, Default: 0x0000
        48. Register Name: config47 - Address: 0x2F, Default: 0x0000
        49. Register Name: config48 - Address: 0x30, Default: 0x0000
        50. Register Name: version- Address: 0x7F, Default: 0x540C (READ ONLY)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 IF Based LTE Transmitter
        1. Design Requirements
        2. Detailed Design Procedure
          1. Data Input Rate
          2. Interpolation
          3. LO Feedthrough and Sideband Correction
        3. Application Curves
      2. 8.2.2 Direct Upconversion (Zero IF) LTE Transmitter
        1. Design Requirements
        2. Detailed Design Procedure
          1. Data Input Rate
          2. Interpolation
          3. LO Feedthrough and Sideband Correction
        3. Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 Assembly
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. Definition of Specifications
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Clarifications for DAC3482 Power Supply and Phase-Locked Loop Specification

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

The design of the PCB is critical to achieve the full performance of the DAC3482 device. Defining the PCB stackup should be the first step in the board design. Experience has shown that at least six layers are required to adequately route all required signals to and from the device. Each signal routing layer must have an adjacent solid ground plane to control signal return paths to have minimal loop areas and to achieve controlled impedances for microstrip and stripline routing. Power planes must also have adjacent solid ground planes to control supply return paths. Minimizing the space between supply and ground planes improves performance by increasing the distributed decoupling.

Although the DAC3482 device consists of both analog and digital circuitry, TI highly recommends solid ground planes that encompass the device and its input and output signal paths. TI does not recommend split ground planes that divide the analog and digital portions of the device. Split ground planes may improve performance if a nearby, noisy, digital device is corrupting the ground reference of the analog signal path. When split ground planes are employed, one must carefully control the supply return paths and keep the paths on top of their respective ground reference planes.

Quality analog output signals and input conversion clock signal path layout is required for full dynamic performance. Symmetry of the differential signal paths and discrete components in the path is mandatory, and symmetrical shunt-oriented components should have a common grounding via. The high frequency requirements of the analog output and clock signal paths necessitate using differential routing with controlled impedances and minimizing signal path stubs (including vias) when possible.

Coupling onto or between the clock and output signals paths should be avoided using any isolation techniques available including distance isolation, orientation planning to prevent field coupling of components like inductors and transformers, and providing well coupled reference planes. Via stitching around the clock signal path and the input analog signal path provides a quiet ground reference for the critical signal paths and reduces noise coupling onto these paths. Sensitive signal traces must not cross other signal traces or power routing on adjacent PCB layers, rather a ground plane must separate the traces. If necessary, the traces should cross at 90° angles to minimize crosstalk.

The substrate (dielectric) material requirements of the PCB are largely influenced by the speed and length of the high speed serial lanes. Affordable and common FR4 varieties are adequate in most cases.

Coupling of ambient signals into the signal path is reduced by providing quiet, close reference planes and by maintaining signal path symmetry to ensure the coupled noise is common-mode. Faraday caging may be used in very noise environment and high dynamic range applications to isolate the signal path.

The following layout guidelines correspond to the layout shown in Figure 100.

  1. DAC output termination resistors should be placed as close to the output pins as possible to provide a DC path to ground and set the source impedance matching.
  2. For DAC on-chip PLL clocking mode, if the external loop filter is not used, leave the loop filter pin floating without any board routing nearby. Signals coupling to this node may cause clock mixing spurs in the DAC output.
  3. Route the high speed LVDS lanes as impedance-controlled, tightly-coupled, differential traces.
  4. Maintain a solid ground plane under the LVDS lanes without any ground plane splits.
  5. Simulation of the LVDS channel with DAC3482 IBIS model is recommended to verify good eye opening of the data patterns.
  6. Keep the OSTR signal routing away from the DACCLK routing to reduce coupling.
  7. Keep routing for RBIAS short, for instance a resistor can be placed on the board directly connecting the RBIAS pin to the ground layer.

The following layout guidelines correspond to the layouts shown in Figure 101 and Figure 102.

  1. Noise power supplies should be routed away from clean supplies. Use two power plane layers, preferably with a ground layer in between.
  2. As shown in Figure 101 and Figure 102, both layers three and four are designated for power supply planes. The DAC analog powers are all in the same layer to avoid coupling with each other, and the planes are copied from layer three to layer four for double the copper coverage area.
  3. Decoupling capacitors should be placed as close to the supply pins as possible. For instance, a capacitor can be placed on the bottom of the board directly connecting the supply pin to a ground layer.

10.2 Layout Examples

DAC3482 top_layer_las748.gifFigure 100. Top Layer of DAC3482 Layout Showing High Speed Signals such as LVDS Bus, DACCLK, OSTR, and DAC Outputs. Layout Example from TSW3085EVM Rev D
DAC3482 3rd_layer_d_las748.gifFigure 101. Third Layer of DAC3482 Layout Showing Power Layers. Layout Example from DAC3482EVM Rev H
DAC3482 4th_layer_las748.gifFigure 102. Fourth Layer of DAC3482 Layout Showing Power Layers. Layout Example from DAC3482EVM Rev H

10.3 Assembly

Information regarding the package and assembly of the WQFN-MR package version of the DAC3482 can be found at the end of the data sheet and also on the following application note: SZZA059

Information regarding the package and assembly of the ZAY package version of the DAC3482 can be found at the end of the data sheet and also on the following application note: SPRAA99