|LEGEND: R/W = Read/Write; R = Read only; -n = value after reset|
|13||SEL_EXTCLK_DIFFSE||R/W||0||Selects the external differential or single ended clock for DACCLK.
0 = differential
1 = single ended
|12||PLL_RESET||R/W||0||When set the M divider; N divider and PFD are held reset|
|11||PLL_NDIVSYNC_ENA||R/W||0||When asserted; the SYSREF input is used to sync the N dividers of the PLL.|
|10||PLL_ENA||R/W||0||Enables the PLL output as the DAC clock when set; the clock provided at the DACCLKP/N is used as the PLL reference clock. When cleared; the PLL is bypassed and the clock provided at the DACCLKP/N pins is used as the DAC clock|
|9||PLL_CP_SLEEP||R/W||1||Must be set to '0' for proper PLL operation.
1 = Charge pump is put to sleep and can be driven by external source through the ATEST pins.
|7:3||PLL_N_M1||R/W||00000||Reference clock divider; divide by is N+1|
|2:0||LOCKDET_ADJ||R/W||000||Adjusts the lock detector sensitivity. Upper bit isn't used:
x00 - highest sensitivity x11 - lowest sensitivity