SLASEQ4A October   2018  – December 2018 DAC43608 , DAC53608

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Block Diagram
      2.      Programmable Window Comparator
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configurations and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2CTM Standard Mode
    7. 7.7  Timing Requirements: I2CTM Fast Mode
    8. 7.8  Timing Requirements: I2CTM Fast+ Mode
    9. 7.9  Timing Requirements: Logic
    10. 7.10 Typical Characteristics: 1.8 V
    11. 7.11 Typical Characteristics: 5.5 V
    12. 7.12 Typical Characteristics
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 8.3.1.1 DAC Transfer Function
        2. 8.3.1.2 DAC Register Update and LDAC Functionality
        3. 8.3.1.3 CLR Functionality
        4. 8.3.1.4 Output Amplifier
      2. 8.3.2 Reference
      3. 8.3.3 Power-on-Reset (POR)
      4. 8.3.4 Software Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 F/S Mode Protocol
      2. 8.5.2 DACx3608 I2CTM Update Sequence
      3. 8.5.3 DACx3608 Address Byte
      4. 8.5.4 DACx3608 Command Byte
      5. 8.5.5 DACx3608 Data Byte (MSDB and LSDB)
      6. 8.5.6 DACx3608 I2CTM Read Sequence
    6. 8.6 Register Map
      1. 8.6.1 DEVICE_CONFIG Register (offset = 01h) [reset = 00FFh]
        1. Table 10. DEVICE_CONFIG Register Field Descriptions
      2. 8.6.2 STATUS/TRIGGER Register (offset = 02h) [reset = 0300h for DAC53608, reset = 0500h for DAC43608]
        1. Table 11. STATUS/TRIGGER Register Field Descriptions
      3. 8.6.3 BRDCAST Register (offset = 03h) [reset = 0000h]
        1. Table 12. BRDCAST Register Field Descriptions
      4. 8.6.4 DACn_DATA Register (offset = 08h to 0Fh) [reset = 0000h]
        1. Table 13. DACn_DATA Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Programmable LED Biasing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Programmable Window Comparator
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

all minimum/maximum specifications at TA = –40°C to +125°C and all typical specification at TA = 25°C, 1.8 V ≤ VDD ≤ 5.5 V, VREFIN = 2.5 V for VDD ≥ 2.7 V, VREFIN = 1.8 V for VDD ≤ 2.7 V, RL= 5 kΩ to AGND, CL = 200 pF to AGND, and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
Resolution DAC53608 10 Bits
DAC43608 8
INL Relative accuracy(1) DAC43608, 2.7 V ≤ VDD ≤ 5.5 V –1 1 LSB
DAC43608, 1.8 V ≤ VDD ≤ 2.7 V –1 1
DAC53608, 2.7 V ≤ VDD ≤ 5.5 V –1 1
DAC53608, 1.8 V ≤ VDD ≤ 2.7 V –1 1
DNL Differential nonlinearity(1) DAC43608, 2.7 V ≤ VDD ≤ 5.5 V –1 1 LSB
DAC43608, 1.8 V ≤ VDD ≤ 2.7 V –1 1
DAC53608, 2.7 V ≤ VDD ≤ 5.5 V –1 1
DAC53608, 1.8 V ≤ VDD ≤ 2.7 V –1 1
Zero code error 2.7 V ≤ VDD ≤ 5.5 V, code 0d into DAC 6 12 mV
1.8 V ≤ VDD ≤ 2.7 V, code 0d into DAC 6 12
Zero code error temperature coefficient ±5 µV/°C
Offset error(1) 2.7 V ≤ VDD ≤ 5.5 V –0.5 0.25 0.5 %FSR
1.8 V ≤ VDD ≤ 2.7 V –0.5 0.25 0.5
Offset error temperature coefficient(1) ±0.0003 %FSR/°C
Gain error(1) 2.7 V ≤ VDD ≤ 5.5 V –0.5 0.25 0.5 %FSR
1.8 V ≤ VDD ≤ 2.7 V –0.5 0.25 0.5
Gain error temperature coefficient(1) ±0.0004 %FSR/°C
Full scale error 2.7 V ≤ VDD ≤ 5.5 V, code 1023d into DAC, no headroom –0.5 0.25 0.5 %FSR
1.8 V ≤ VDD ≤ 2.7 V, code 1023d into DAC, no headroom –1 0.5 1
Full scale error temperature coefficient ±0.0004 %FSR/°C
OUTPUT CHARACTERISTICS
VOUTX Output voltage 0 5.5 V
CL Capacitive load(2) RL = Infinite 1 nF
RL = 5 kΩ 2
Load regulation DAC at midscale, -10 mA ≤ IOUT ≤ 10 mA, VDD = 5.5 V 0.1 mV/mA
Short circuit current VDD = 1.8 V, (per channel) full-scale output shorted to AGND or zero-scale output shorted to VDD 10 mA
VDD = 2.7 V, (per channel) full-scale output shorted to AGND or zero-scale output shorted to VDD 25
VDD = 5.5 V, (per channel) full-scale output shorted to AGND or zero-scale output shorted to VDD 50
Output voltage headroom to VDD (DAC output unloaded) 0.05 V
Output voltage headroom(2) to VDD (load current = 10 mA@VDD = 5.5 V, load current = 3 mA@VDD = 2.7 V, load current = 1 mA@VDD = 1.8 V), DAC code = full Scale 10 %FSR
ZO DC output impedance DAC at midscale 0.25 Ω
DAC at code 4d 0.25
DAC at code 1016 0.26
DC-PSRR Power supply rejection ratio (DC) DAC at midscale; VDD = 5 V ± 10% 0.25 mV/V
DYNAMIC PERFORMANCE
tsett Output voltage settling time 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, RL = 5 kΩ, CL = 200 pF, VDD = 5.5 V 10 µs
SR Slew rate RL = 5 kΩ, CL = 200 pF, VDD = 5.5 V 0.6 V/µs
Power on glitch magnitude RL = 5 kΩ, CL = 200 pF 110 mV
Vn Output noise 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V 40 µVpp
Vn Output noise 0.1 Hz to 100 kHz bandwidth, DAC at midscale, VDD = 5.5 V 0.05 mVrms
Vn Output noise density measured at 1 kHz, DAC at midscale, VDD = 5.5 V 0.2 µV/√Hz
measured at 10 kHz, DAC at midscale, VDD = 5.5 V 0.2
AC-PSRR Power supply rejection ratio (AC) 200 mV 50/60 Hz sine wave superimposed on power supply voltage, DAC at midscale –71 dB
Channel-to-channel AC crosstalk Full-scale swing on adjacent channel 1.5 nV-s
Channel-to-channel DC crosstalk Full-scale swing on all channel, measured channel at zero or full scale 0.05 LSB
Code change glitch impulse ±1 LSB change around mid code (including feedthrough) 10 nV-s
Code change glitch impulse magnitude ±1 LSB change around mid code (including feedthrough) 25 mV
VOLTAGE REFERENCE INPUT
Reference input impedance All channel powered on 12.5 kΩ
Reference input capacitance 50 pF
DIGITAL INPUTS
Digital feedthrough At SCLK = 1 MHz, DAC output static at mid scale 20 nV-s
Pin capacitance Per pin 10 pF
POWER REQUIREMENTS
IVDD Current flowing into VDD Normal mode, all DACs at full scale. SPI static. 3 5 mA
IVDD Current flowing into VDD All DACs power-down 50 µA
(1) End point fit between codes Code 4 to Code 1016 for 10 bit, Code 1 to Code 251 for 8 bit
(2) Not production tested