SLASEQ4A October   2018  – December 2018 DAC43608 , DAC53608

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Block Diagram
      2.      Programmable Window Comparator
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configurations and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2CTM Standard Mode
    7. 7.7  Timing Requirements: I2CTM Fast Mode
    8. 7.8  Timing Requirements: I2CTM Fast+ Mode
    9. 7.9  Timing Requirements: Logic
    10. 7.10 Typical Characteristics: 1.8 V
    11. 7.11 Typical Characteristics: 5.5 V
    12. 7.12 Typical Characteristics
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 8.3.1.1 DAC Transfer Function
        2. 8.3.1.2 DAC Register Update and LDAC Functionality
        3. 8.3.1.3 CLR Functionality
        4. 8.3.1.4 Output Amplifier
      2. 8.3.2 Reference
      3. 8.3.3 Power-on-Reset (POR)
      4. 8.3.4 Software Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 F/S Mode Protocol
      2. 8.5.2 DACx3608 I2CTM Update Sequence
      3. 8.5.3 DACx3608 Address Byte
      4. 8.5.4 DACx3608 Command Byte
      5. 8.5.5 DACx3608 Data Byte (MSDB and LSDB)
      6. 8.5.6 DACx3608 I2CTM Read Sequence
    6. 8.6 Register Map
      1. 8.6.1 DEVICE_CONFIG Register (offset = 01h) [reset = 00FFh]
        1. Table 10. DEVICE_CONFIG Register Field Descriptions
      2. 8.6.2 STATUS/TRIGGER Register (offset = 02h) [reset = 0300h for DAC53608, reset = 0500h for DAC43608]
        1. Table 11. STATUS/TRIGGER Register Field Descriptions
      3. 8.6.3 BRDCAST Register (offset = 03h) [reset = 0000h]
        1. Table 12. BRDCAST Register Field Descriptions
      4. 8.6.4 DACn_DATA Register (offset = 08h to 0Fh) [reset = 0000h]
        1. Table 13. DACn_DATA Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Programmable LED Biasing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Programmable Window Comparator
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.2 Detailed Design Procedure

Figure 66 provides an example in which single DAC channel is used to compare both high and low thresholds. A dual comparator is used per DAC channel as shown. A voltage divider formed by resistors RA and RB are used in order to bring the signal level within the DAC range. Another pair of resistors R1 and R2 are used for setting the low threshold as a factor of the high threshold. This configuration allows the use of a single DAC channel for monitoring both high and low threshold levels. The comparators should be open-drain in order to provide the following advantages.

  • Generate a logic output level suitable for the monitoring processor
  • Allow shorting of the two outputs in order to generate a single trigger

In the circuit depicted in Figure 66 the output of the circuit remains HIGH as long as the signal input remains within the high and low threshold levels. Upon violation of any one threshold, the output goes LOW. Equation 3 provides the derivation of the low threshold voltage from the high threshold set by the DAC.

Equation 3. DAC53608 DAC43608 dacx3608-comparator-eq.gif

In order to monitor a power supply of 5 V within ±10%, it is recommended to place the nominal value at the DAC mid code. The output range of DACx3608 to be 0 – 5 V, thus the mid code voltage output is 2.5 V. Hence, RA and RB can be chosen in such a way that the voltage to be compared is 2.5 V. For this example, RA is equal to RB and we can use 10-kΩ resistors for both of them. One channel of the DACx3608 must be programmed to VTHLD-HI, for example 2.5 V + 5% = 2.625 V. This corresponds to a 10-bit DAC code of (210÷5 V) × 2.625 V = 537.6 (0x21 Ah). In order to generate VTHLD-LO(for example, 2.5 V – 5% = 2.405 V) from 2.625 V, the values of R1 and R2 can be calculated as 7.5 kΩ and 82 kΩ, respectively using Equation 3. The pseudocode for getting started with the programmable window comparator application with the desired DAC value is given below.


//SYNTAX: WRITE <REGISTER NAME(Hex Code)>, <DATA>
//Power-up the device and channels
WRITE DEVICE_CONFIG(0x01), 0x0000
//Program 2.625V on channel A
WRITE DACA_DATA(0x08), 0x0868 //10-bit MSB aligned