SLASEY5 December   2020 DAC43701 , DAC53701

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2C Standard Mode
    7. 7.7  Timing Requirements: I2C Fast Mode
    8. 7.8  Timing Requirements: I2C Fast Mode Plus
    9. 7.9  Timing Requirements: GPI
    10. 7.10 Timing Diagram
    11. 7.11 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
    12. 7.12 Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
    13. 7.13 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 8.3.1.1 Reference Selection and DAC Transfer Function
          1. 8.3.1.1.1 Power Supply as Reference
          2. 8.3.1.1.2 Internal Reference
      2. 8.3.2 General-Purpose Input (GPI)
      3. 8.3.3 DAC Update
        1. 8.3.3.1 DAC Update Busy
      4. 8.3.4 Nonvolatile Memory (EEPROM or NVM)
        1. 8.3.4.1 NVM Cyclic Redundancy Check
        2. 8.3.4.2 NVM_CRC_ALARM_USER Bit
        3. 8.3.4.3 NVM_CRC_ALARM_INTERNAL Bit
      5. 8.3.5 Programmable Slew Rate
      6. 8.3.6 Power-on-Reset (POR)
      7. 8.3.7 Software Reset
      8. 8.3.8 Device Lock Feature
      9. 8.3.9 PMBus Compatibility
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Down Mode
      2. 8.4.2 Continuous Waveform Generation (CWG) Mode
      3. 8.4.3 PMBus Compatibility Mode
      4. 8.4.4 Medical Alarm Generation Mode
        1. 8.4.4.1 Low-Priority Alarm
        2. 8.4.4.2 Medium-Priority Alarm
        3. 8.4.4.3 High-Priority Alarm
        4. 8.4.4.4 Interburst Time
        5. 8.4.4.5 Pulse Off Time
        6. 8.4.4.6 Pulse On Time
    5. 8.5 Programming
      1. 8.5.1 F/S Mode Protocol
      2. 8.5.2 I2C Update Sequence
        1. 8.5.2.1 Address Byte
          1. 8.5.2.1.1 Slave Address Configuration
        2. 8.5.2.2 Command Byte
      3. 8.5.3 I2C Read Sequence
    6. 8.6 Register Map
      1. 8.6.1  STATUS Register (address = D0h) [reset = 000Ch or 0014h]
      2. 8.6.2  GENERAL_CONFIG Register (address = D1h) [reset = 01F0h]
      3. 8.6.3  CONFIG2 Register (address = D2h) [reset = 0000h]
      4. 8.6.4  TRIGGER Register (address = D3h) [reset = 0008h]
      5. 8.6.5  DAC_DATA Register (address = 21h) [reset = 0000h]
      6. 8.6.6  DAC_MARGIN_HIGH Register (address = 25h) [reset = 0000h]
      7. 8.6.7  DAC_MARGIN_LOW Register (address = 26h) [reset = 0000h]
      8. 8.6.8  PMBUS_OPERATION Register (address = 01h) [reset = 0000h]
      9. 8.6.9  PMBUS_STATUS_BYTE Register (address = 78h) [reset = 0000h]
      10. 8.6.10 PMBUS_VERSION Register (address = 98h) [reset = 2200h]
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Appliance Light Fade-In Fade-Out
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Power-Supply Margining
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Medical Alarm Generation
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Design Procedure

Choose a small VSET so that the power dissipation across RSET is minimum. Choose 1 V for the bright condition, which results in an RSET of (1 V / 20 mA) = 50 Ω. Set the DACx3701 output span to 1.8 V. The output buffer of the DAC is connected in a force-sense configuration to the MOSFET, as shown in Figure 9-1. This configuration compensates the gate-source voltage drop caused by temperature, drain current, and ageing of the MOSFET. Considering a typical gate-source voltage of 1.2 V and a power supply headroom of 200 mV, the VDD for the DAC must be a minimum of (1 V + 1.2 V + 200 mV) = 2.4 V. Use a standard 3.3-V or 5-V power supply for the DAC. A bipolar junction transistor (BJT) provides a much smaller base-emitter voltage drop, but a MOSFET has better matching between the drain and source currents. Choose a BJT over the MOSFET in case there is a less than 2.4-V supply voltage available for the DAC. Configure the MARGIN HIGH value to the code equivalent of 1 V; that is (1 V / 1.8 V) × 1024 = 569d or 0x239. The MARGIN LOW value should be the equivalent of the dim LED current that is 10 mA, which corresponds to a DAC voltage of (10 mA × 50 Ω) = 500 mV. The code for MARGN LOW is (500 mV / 1.8 V) × 1024 = 284d or 0x11C.

For control without the use of software, map the GPI to margin high-low operation as listed in Table 8-1. The rising edge of the GPI maps to the MARGIN HIGH value of the 20-mA LED current, and the falling edge maps to the MARGIN LOW value of the 10-mA LED current. When the DAC output is in the slewing condition, any change in the GPI state changes the direction of the slew after the ongoing SLEW_RATE time, as shown in the Section 9.2.1.3 section.

The slew time is given by (MARGIN_HIGH – MARGIN_LOW) × CODE_STEP × SLEW_RATE. For a 1.5-s slew time, CODE_STEP × SLEW_RATE = 1.5 / (569 – 284) = ~ 5 ms. Choose the CODE_STEP as 1 LSB and SLEW_RATE of 4.9152 ms. This configuration provides a slew time of 1.4 s. Adjust the MARGIN HIGH and MARGIN LOW values for more granular control.

The following pseudocode helps to get started with a light fade-in fade-out application:

//SYNTAX: WRITE <REGISTER NAME (Hex code)>, <MSB DATA>, <LSB DATA>
//Write MARGIN-HIGH code (12-bit aligned) for bright LED light
//For a 1.8-V output range, the 10-bit hex code for 1 V is 0x0239.
//With 12-bit alignment, it becomes 0x08E4
WRITE DAC_MARGIN_HIGH(0x25), 0x08, 0xE4
//Write MARGIN-LOW code (12-bit aligned) for dim LED light
//For a 1.8-V output range, the 10-bit hex code for 500 mV is 0x11C. 
//With 12-bit alignment, it becomes 0x0470
WRITE DAC_MARGIN_LOW(0x26), 0x04, 0x70
//Map GPI to margin high-low function
WRITE CONFIG2(0xD2), 0x10, 0x00
//Enable GPI
WRITE TRIGGER(0xD3), 0x04, 0x08
//Configure internal reference with 1.5x output span, and slew time and power-up the device
//CODE_STEP: 1 LSB, SLEW_RATE: 4.9152 ms
WRITE GENERAL_CONFIG(0xD1), 0x01, 0x64
//Program the EEPROM
WRITE TRIGGER(0xD3), 0x04, 0x18