SLAS536D September   2007  – November 2021 DAC5662A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Resistance Characteristics
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics
    7. 6.7  Electrical Characteristics, AC
    8. 6.8  Electrical Characteristics, DC
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Digital Inputs and Timing
      1. 7.1.1 Digital Inputs
      2. 7.1.2 Input Interfaces
      3. 7.1.3 Dual-Bus Data Interface and Timing
      4. 7.1.4 Single-Bus Interleaved Data Interface and Timing
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Transfer Function
      2. 8.3.2 Analog Outputs
      3. 8.3.3 Output Configurations
      4. 8.3.4 Differential With Transformer
      5. 8.3.5 Single-Ended Configuration
      6. 8.3.6 Reference Operation
        1. 8.3.6.1 Internal Reference
        2. 8.3.6.2 External Reference
      7. 8.3.7 Gain Setting Option
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
  9. 9 Application and Implementation
    1. 9.1 Application Informmation
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1.3 Dual-Bus Data Interface and Timing

In dual-bus mode, the MODE pin is connected to DVDD. The two converter channels within the DAC5662A consist of two independent, 12-bit, parallel data ports. Each DAC channel is controlled by its own set of write (WRTA, WRTB) and clock (CLKA, CLKB) lines. The WRT lines control the channel input latches and the CLK lines control the DAC latches. The data is first loaded into the input latch by a rising edge of the WRT line

The internal data transfer requires a correct sequence of write and clock inputs, since essentially two clock domains having equal periods (but possibly different phases) are input to the DAC5662A. This is defined by a minimum requirement of the time between the rising edge of the clock and the rising edge of the write inputs. This essentially implies that the rising edge of CLK must occur at the same time or before the rising edge of the WRT signal. A minimum delay of 2 ns should be maintained if the rising edge of the clock occurs after the rising edge of the write. Note that these conditions are satisfied when the clock and write inputs are connected externally. Note that all specifications were measured with the WRT and CLK lines connected together.

GUID-E1A5232B-8888-4851-BF88-6D6202FEC7ED-low.gifFigure 7-3 Dual Bus Mode Operation