The DACx0508 includes a power-on reset function that controls the output voltage at power up. After the VDD and VIO supplies have been established a POR event is issued. The POR causes all registers to initialize to their default values and communication with the device is valid only after a 250 µs power-on-reset delay. The default value for all DACs in the DACx0508Z devices is zero-code and midscale-code for the DACx0508M ones. Each DAC channel remains at the power-up voltage until a valid command is written to it.
The POR circuit requires specific supply levels to discharge the internal capacitors and to reset the device on power up, as indicated in Figure 62 and Figure 63. In order to ensure a POR event, VDD or VIO must be below their corresponding low thresholds for at least 100 µs. If VDD and VIO remain above their specified high threshold a POR event will not occur. When the supplies drop below their high threshold but remain over the lower one (shown as the undefined region), the device may or may not reset under all specified temperature and power-supply conditions.