Table 7-2 shows that comparator mode provides hysteresis when the CMP-X-MODE bit is set to 01b. Figure 7-5 shows that the hysteresis is provided by the DAC-X-MARGIN-HIGH and DAC-X-MARGIN-LOW registers.
When the DAC-X-MARGIN-HIGH is set to full-code or the DAC-X-MARGIN-LOW is set to zero-code, the comparator works as a latching comparator; that is, the output is latched after the threshold is crossed. The latched output can be reset by writing to the corresponding RST-CMP-FLAG-X bit in the COMMON-DAC-TRIG register. Figure 7-6 shows the behavior of a latching comparator with active low output, and Figure 7-7 shows the behavior of a latching comparator with active high output.