The following steps explain a complete
transaction in F/S mode.
- The controller initiates data transfer by generating a start condition. Figure 7-19 shows that the start condition is when a high-to-low transition occurs on the
SDA line while SCL is high. All I2C-compatible devices recognize a
- The controller then generates the SCL pulses, and transmits the 7-bit address
and the read/write direction bit (R/W) on the SDA line.
During all transmissions, the controller makes sure that data are valid. Figure 7-20 shows that a valid data condition requires the SDA line to be stable during
the entire high period of the clock pulse. All devices recognize the address
sent by the controller and compare the address to the respective internal fixed
address. Only the target device with a matching address generates an acknowledge
by pulling the SDA line low during the entire high period of the 9th SCL cycle
(see also Figure 7-18). When the controller detects this acknowledge, the communication link with a
target has been established.
- The controller generates further SCL cycles to transmit
(R/W bit 0) or receive (R/W bit 1)
data to the target. In either case, the receiver must acknowledge the data sent
by the transmitter. The acknowledge signal can be generated by the controller or
by the target, depending on which is the receiver. The 9-bit valid data
sequences consists of eight data bits and one acknowledge-bit, and can continue
as long as necessary.
- Figure 7-19 shows that to signal the end of the data transfer, the controller generates a
stop condition by pulling the SDA line from low-to-high while the SCL line is
high. This action releases the bus and stops the communication link with the
addressed target. All I2C-compatible devices recognize the stop
condition. Upon receipt of a stop condition, the bus is released, and all target
devices then wait for a start condition followed by a matching address.
Figure 7-19 Start and Stop
Conditions Figure 7-20 Bit Transfer on the