SLASEH2
November 2020
DAC81404
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements: Write, IOVDD: 1.7 V to 2.7 V
6.7
Timing Requirements: Write, IOVDD: 2.7 V to 5.5 V
6.8
Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 1.7 V to 2.7 V
6.9
Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 1.7 V to 2.7 V
6.10
Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 2.7 V to 5.5 V
6.11
Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 2.7 V to 5.5 V
6.12
Timing Diagrams
6.13
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
R-2R Ladder DAC
7.3.2
Programmable-Gain Output Buffer
7.3.2.1
Sense Pins
7.3.3
DAC Register Structure
7.3.3.1
DAC Output Update
7.3.3.1.1
Synchronous Update
7.3.3.1.2
Asynchronous Update
7.3.3.2
Broadcast DAC Register
7.3.3.3
Clear DAC Operation
7.3.4
Internal Reference
7.3.5
Power-On Reset (POR)
7.3.5.1
Hardware Reset
7.3.5.2
Software Reset
7.3.6
Thermal Alarm
7.4
Device Functional Modes
7.4.1
Power-Down Mode
7.5
Programming
7.5.1
Stand-Alone Operation
7.5.2
Daisy-Chain Operation
7.5.3
Frame Error Checking
7.6
Register Map
7.6.1
NOP Register (address = 00h) [reset = 0000h]
7.6.2
DEVICEID Register (address = 01h) [reset = 0A60h]
7.6.3
STATUS Register (address = 02h) [reset = 0000h]
7.6.4
SPICONFIG Register (address = 03h) [reset = 0AA4h]
7.6.5
GENCONFIG Register (address = 04h) [reset = 4000h]
7.6.6
BRDCONFIG Register (address = 05h) [reset = 000Fh]
7.6.7
SYNCCONFIG Register (address = 06h) [reset = 0000h]
7.6.8
DACPWDWN Register (address = 09h) [reset = FFFFh]
7.6.9
DACRANGE Register (address = 0Ah) [reset = 0000h]
7.6.10
TRIGGER Register (address = 0Eh) [reset = 0000h]
7.6.11
BRDCAST Register (address = 0Fh) [reset = 0000h]
7.6.12
DACn Register (address = 10h to 13h) [reset = 0000h]
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Receiving Notification of Documentation Updates
11.3
Support Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RHB|32
MPQF130D
Thermal pad, mechanical data (Package|Pins)
RHB|32
QFND029X
Orderable Information
slaseh2_oa
slaseh2_pm
1
Features
Performance:
Specified monotonic at 16-bit resolution
INL: ±1 LSB maximum at 16-bit resolution
TUE: ±0.05% FSR, maximum
Integrated output buffer
Full-scale output voltage: ±5 V, ±10 V, ±20 V, 5 V, 10 V, 20 V, 40 V
High drive capability: ±15 mA
Per channel sense pins
Integrated 2.5-V precision reference
Initial accuracy: ±2.5 mV, maximum
Low drift: 10 ppm/°C, maximum
Reliability features:
CRC error check
Short circuit limit
Fault pin
50-MHz, SPI-compatible serial interface
4-wire mode, 1.7-V to 5.5-V operation
Readback and daisy-chain operations
Temperature range: –40°C to +125°C
Package: 5-mm × 5-mm, 32-pin QFN