SLASEH2 November   2020 DAC81404

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Write, IOVDD: 1.7 V to 2.7 V
    7. 6.7  Timing Requirements: Write, IOVDD: 2.7 V to 5.5 V
    8. 6.8  Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 1.7 V to 2.7 V
    9. 6.9  Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 1.7 V to 2.7 V
    10. 6.10 Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 2.7 V to 5.5 V
    11. 6.11 Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 2.7 V to 5.5 V
    12. 6.12 Timing Diagrams
    13. 6.13 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 R-2R Ladder DAC
      2. 7.3.2 Programmable-Gain Output Buffer
        1. 7.3.2.1 Sense Pins
      3. 7.3.3 DAC Register Structure
        1. 7.3.3.1 DAC Output Update
          1. 7.3.3.1.1 Synchronous Update
          2. 7.3.3.1.2 Asynchronous Update
        2. 7.3.3.2 Broadcast DAC Register
        3. 7.3.3.3 Clear DAC Operation
      4. 7.3.4 Internal Reference
      5. 7.3.5 Power-On Reset (POR)
        1. 7.3.5.1 Hardware Reset
        2. 7.3.5.2 Software Reset
      6. 7.3.6 Thermal Alarm
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Down Mode
    5. 7.5 Programming
      1. 7.5.1 Stand-Alone Operation
      2. 7.5.2 Daisy-Chain Operation
      3. 7.5.3 Frame Error Checking
    6. 7.6 Register Map
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DEVICEID Register (address = 01h) [reset = 0A60h]
      3. 7.6.3  STATUS Register (address = 02h) [reset = 0000h]
      4. 7.6.4  SPICONFIG Register (address = 03h) [reset = 0AA4h]
      5. 7.6.5  GENCONFIG Register (address = 04h) [reset = 4000h]
      6. 7.6.6  BRDCONFIG Register (address = 05h) [reset = 000Fh]
      7. 7.6.7  SYNCCONFIG Register (address = 06h) [reset = 0000h]
      8. 7.6.8  DACPWDWN Register (address = 09h) [reset = FFFFh]
      9. 7.6.9  DACRANGE Register (address = 0Ah) [reset = 0000h]
      10. 7.6.10 TRIGGER Register (address = 0Eh) [reset = 0000h]
      11. 7.6.11 BRDCAST Register (address = 0Fh) [reset = 0000h]
      12. 7.6.12 DACn Register (address = 10h to 13h) [reset = 0000h]
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • Performance:
    • Specified monotonic at 16-bit resolution
    • INL: ±1 LSB maximum at 16-bit resolution
    • TUE: ±0.05% FSR, maximum
  • Integrated output buffer
    • Full-scale output voltage: ±5 V, ±10 V, ±20 V, 5 V, 10 V, 20 V, 40 V
    • High drive capability: ±15 mA
    • Per channel sense pins
  • Integrated 2.5-V precision reference
    • Initial accuracy: ±2.5 mV, maximum
    • Low drift: 10 ppm/°C, maximum
  • Reliability features:
    • CRC error check
    • Short circuit limit
    • Fault pin
  • 50-MHz, SPI-compatible serial interface
    • 4-wire mode, 1.7-V to 5.5-V operation
    • Readback and daisy-chain operations
  • Temperature range: –40°C to +125°C
  • Package: 5-mm × 5-mm, 32-pin QFN