If the DACx760 is used in a noisy environment, error checking can be used to check the integrity of SPI data communication between the device and the host processor. This feature can be enabled by setting the CRCEN bit of the Configuration Register to 1. The frame error checking scheme is based on the CRC-8-ATM (HEC) polynomial x8 + x2 + x + 1 (that is, 100000111). When error checking is enabled, the SPI frame width is 32 bits, as shown in Table 8-4. Start with the default 24-bit frame and enable frame error checking through the CRCEN bit and switch to the 32-bit frame. The normal 24-bit SPI data are appended with an 8-bit CRC polynomial by the host processor before feeding it to the device. For a register readback, the CRC polynomial is output on the SDO pins by the device as part of the 32-bit frame.
|BIT 31:BIT 8||BIT 7:BIT 0|
|Normal SPI frame data||8-bit CRC polynomial|
When in CRC mode, the DACx760 calculates CRC words every 32-clocks, unconditional of when the LATCH pin toggles. The DACx760 decodes the 32-bit input frame data to compute the CRC remainder. If no error exists in the frame, the CRC remainder is zero. When the remainder is non-zero (that is, the input frame has single- or multiple-bit errors), the ALARM pin asserts low and the CRC-FLT bit of the status register is also set to 1. The ALARM pin can be asserted low for any of the different conditions, as explained in Section 8.3.8. To reset the CRC-FLT bit to 0, use a software reset command of 0x96, disable the frame error checking, or power down the device. In the case of a CRC error, the specific SPI frame is blocked from writing to the device.
If CRC mode is enabled on the first frame issued to the device after power up, issue a no operation (NOOP) command to the device to reset the SPI clock and SPI frame alignment in the event that any transients on the SCLK line are interpreted as SCLK periods. To issue a NOOP command to the device, simply toggle the LATCH pin without any SCLK periods.