SBAS528C June   2013  – January 2018 DAC7760 , DAC8760

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: AC
    7. 7.7  Timing Requirements: Write Mode
    8. 7.8  Timing Requirements: Readback Mode
    9. 7.9  Timing Requirements: Daisy-Chain Mode
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  DAC Architecture
      2. 8.3.2  Voltage Output Stage
      3. 8.3.3  Current Output Stage
      4. 8.3.4  Internal Reference
      5. 8.3.5  Digital Power Supply
      6. 8.3.6  DAC Clear
      7. 8.3.7  Power-Supply Sequence
      8. 8.3.8  Power-On Reset
      9. 8.3.9  Alarm Detection
      10. 8.3.10 Watchdog Timer
        1. 8.3.10.1 The DACx760 Shares the SPI Bus With Other Devices (Non-DACx760)
      11. 8.3.11 Frame Error Checking
        1. 8.3.11.1 The DACx760 Shares the SPI Bus With Other Devices (Non-DACx760)
      12. 8.3.12 User Calibration
      13. 8.3.13 Programmable Slew Rate
    4. 8.4 Device Functional Modes
      1. 8.4.1 Setting Voltage and Current Output Ranges
      2. 8.4.2 Boost Configuration for IOUT
      3. 8.4.3 Filtering the Current Output (only on the VQFN package)
      4. 8.4.4 HART Interface
        1. 8.4.4.1 For 4-mA to 20-mA Mode
        2. 8.4.4.2 For All Current Output Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI)
        1. 8.5.1.1 SPI Shift Register
        2. 8.5.1.2 Write Operation
        3. 8.5.1.3 Read Operation
        4. 8.5.1.4 Stand-Alone Operation
        5. 8.5.1.5 Daisy-Chain Operation
    6. 8.6 Register Maps
      1. 8.6.1 DACx760 Commands and Register Map
        1. 8.6.1.1 DACx760 Register Descriptions
          1. 8.6.1.1.1 Control Register
          2. 8.6.1.1.2 Configuration Register
          3. 8.6.1.1.3 DAC Registers
          4. 8.6.1.1.4 Reset Register
          5. 8.6.1.1.5 Status Register
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Controlling the VOUT and IOUT Pins
        1. 9.1.1.1 VOUT and IOUT Pins are Independent Outputs, Never Simultaneously Enabled
        2. 9.1.1.2 VOUT and IOUT Pins are Independent Outputs, Simultaneously Enabled
        3. 9.1.1.3 VOUT and IOUT Pins are Tied Together, Never Simultaneously Enabled
      2. 9.1.2 Implementing HART in All Current Output Modes
        1. 9.1.2.1 Using CAP2 Pin on VQFN Package
        2. 9.1.2.2 Using the ISET-R Pin
      3. 9.1.3 Short-Circuit Current Limiting
    2. 9.2 Typical Application
      1. 9.2.1 Voltage and Current Output Driver for Factory Automation and Control, EMC and EMI Protected
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

Controlling the VOUT and IOUT Pins

This section describes how to control the VOUT and IOUT pins for three use cases:

VOUT and IOUT Pins are Independent Outputs, Never Simultaneously Enabled

In most applications, VOUT and IOUT are not connected together. In addition, only one is enabled at a time or they are both powered down. In this configuration, bits 10 down to 7 of the Configuration Register must be set to 0000 (default value). Bits 2 down to 0 of the Control Register (RANGE bits) control VOUT and IOUT.

VOUT and IOUT Pins are Independent Outputs, Simultaneously Enabled

When VOUT and IOUT are independent outputs and simultaneously enabled, bit 8 of the Configuration Register (DUAL OUTEN) must be set to 1. Bits 2 down to 0 of the Control Register (RANGE bits) control VOUT and bits 10 down to 9 of the Configuration Register (IOUT RANGE) control IOUT. Note that only one DAC code register exists and therefore the voltage and current outputs are controlled by the same code. Note that changing the RANGE bits at any time causes the DAC data register to be cleared based on the value of the CLR-SEL pin or CLRSEL register bit and the new value of the RANGE bits.

VOUT and IOUT Pins are Tied Together, Never Simultaneously Enabled

When the VOUT and IOUT pins are tied together, bit 8 of the Configuration Register (DUAL OUTEN) must be set to 0. Bits 2 down to 0 of the Control Register (RANGE) control VOUT and IOUT. Special consideration must be paid to the +VSENSE pin in this case. When VOUT is disabled, the +VSENSE pin is connected to the internal amplifier input through an internal 60-kΩ resistor as shown in Figure 83. This internal node has diode clamps to REFIN and GND. Setting bit 6 of the Configuration Register (APD) forces this internal node to be tied to GND through a 10-kΩ resistor, in effect, the +VSENSE pin is tied to GND through a 70-kΩ power-down resistor. Figure 91 shows the leakage current into the +VSENSE pin for both settings of the APD bit.

DAC7760 DAC8760 VSENSE_P_Leakage_plot.png Figure 91. +VSENSE Leakage Current vs Pin Voltage

Whether the APD bit is set or not set, the current output in this case incurs a gain error because the internal resistor acts as a parallel load in addition to the external load. If this gain error is undesirable, it can be corrected through the gain calibration register shown in Table 22. Another option is to use the application circuit in Figure 92.

DAC7760 DAC8760 V_I_Connect_bas528.gif Figure 92. VOUT and IOUT Tied Together to One Terminal

The buffer amplifier prevents leakage through the internal 60-kΩ resistor in current output mode and does not allow it to be seen as a parallel load. The VOUT pin is in high impedance mode in this case and allows minimal leakage current. Note that the offset of the external amplifier adds to the overall VOUT offset error and any potential phase shift from the external amplifier can cause VOUT stability issues.

Implementing HART in All Current Output Modes

If it is desirable to implement HART irrespective of the RANGE bit settings, there are two ways to do this.

Using CAP2 Pin on VQFN Package

The first method of implementing HART is to couple the signal through the CAP2 pin, as conceptualized in Figure 93. Note that this pin is only available in the 40-pin VQFN package.

DAC7760 DAC8760 V_2_I_Conv_CAP_1_2_bas528.gif Figure 93. Implementing HART on IOUT Using the CAP2 Pin

In Figure 93, R3 is nominally 40 Ω, and R2 is dependent on the current output range (set by the RANGE bits) as described below:

  • 4-mA to 20-mA range: R2 = 2.4 kΩ typical
  • 0-mA to 20-mA range: R2 = 3 kΩ typical
  • 0-mA to 24-mA range: R2 = 3.6 kΩ typical

The purpose of the 12.5-kΩ resistor is to create a filter when CAP1 and CAP2 are used.

To insert the external HART signal on the CAP2 pin, an external ac-coupling capacitor is typically connected to CAP2. The high-pass filter 3-dB frequency would be determined by the resistive impedance looking into CAP2 (R2 + 12.5 kΩ) and the coupling capacitor value. The 3-dB frequency would be 1 /(2 × π × [R2 + 12.5 kΩ] × [Coupling Cap Value]).

After the input HART frequency is greater than the 3-dB frequency, the ac signal is seen at the plus input of amplifier A2 and would therefore be seen across the 40-Ω resistor. To generate a 1-mA signal on the output would therefore require a 40-mV peak-to-peak signal on CAP2. Because most HART modems do not output a 40-mV signal, a capacitive divider is used in the above circuit to attenuate the FSK signal from the modem. In the above circuit, the high-pass cutoff frequency would be 1 / (2 × π × [R2+12.5 kΩ] × [C1 + C2]). There is one disadvantage of this approach: if the AVDD supply was not clean, any ripple on it could couple into the part.

Using the ISET-R Pin

The second method to implement HART is to couple the HART signal through the ISET-R pin when IOUT is operated using an external RSET resistor. The FSK signal from the modem is ac coupled into the pin through a series combination of Rin and Cin as shown in Figure 94.

DAC7760 DAC8760 ISET_R_block_diagram.gif Figure 94. Implementing HART With the ISET-R pin

The magnitude of the ac current output is calculated as (VHART × k) / Rin, where k is a constant that represents the gain transfer function from the ISET-R pin to the IOUT pin and depends on the selected current output range as follows: k = 60 for the 4-mA to 20-mA range, 75 for the 0-mA to 20-mA range, and 90 for the 0-mA to 24-mA range. The series input resistor and capacitor form a high-pass filter at the ISET-R pin and Cin must be selected to make sure that all signals in the HART extended-frequency band pass through unattenuated.

Short-Circuit Current Limiting

The DACx760 voltage output includes an internal circuit to typically regulate the load current to about 30 mA. However, this parameter is not production tested or trimmed. Optionally, users can use an external current limiting circuit on VOUT. However, if the VOUT, IOUT and +VSENSE pins are tied together, this circuit must be placed in the VOUT path before it is tied together to the other pins at the common terminal. The nature of the current-limiting circuit depends on the application and load. An example of a unidirectional current limiter is shown in Figure 95.

DAC7760 DAC8760 Unidirectional_ILimit_bas528.gif Figure 95. Unidirectional Current Limiter Circuit

Under normal operation, most current in this circuit flows through Q1 and into R3. As current increases through R3, so does the voltage drop across R3, which increases the base-emitter voltage of Q2. Eventually the base-emitter voltage of Q2 becomes high enough to turn on Q2, which turns off Q1 and reduce the current that can pass from VIN to VOUT. The value of R3 sets the current limit. Note that this is a very simple example and only applies for sourcing current into a resistive load. For cases involving both sourcing and sinking current as well as nonresistive loads, more complex circuits are required to achieve bidirectional current limiting.

Typical Application

Voltage and Current Output Driver for Factory Automation and Control, EMC and EMI Protected

DAC7760 DAC8760 DAC8760_App_Circ_01_bas528.gif Figure 96. DACx760 in an Analog Output (AO) Module

Design Requirements

Analog I/O modules are used by programmable logic controllers (PLCs) and distributed control systems (DCSs) to interface to sensors, actuators, and other field instruments. These modules must meet stringent electrical specifications for both performance as well as protection. These outputs are typically current loops based on the 4-mA to 20-mA range and derivatives or voltage outputs ranging from 0 V to 5 V, 0 V to 10 V, ±5 V, and ±10 V. Common error budgets accommodate 0.1% full-scale range total unadjusted error (% FSR TUE) at room temperature. Designs that desire stronger accuracy over temperature frequently implement calibration. Often times the PLC back-plane provides access to a 12-V to 36-V analog supply from which a majority of supply voltages are derived.

Detailed Design Procedure

DAC7760 DAC8760 general_circuit_sbas528.gif Figure 97. Generic Design for Typical PLC Current and Voltage Outputs

Figure 97 illustrates a common generic solution for realizing these desired voltage and current output spans.

The current output circuit is comprised of amplifiers A1 and A2, MOSFETs Q1 and Q1, and the three resistors RSET, RA, and RB. This two-stage current source enables the ground-referenced DAC output voltage to drive the high-side amplifier required for the current-source.

The voltage output circuit is composed of amplifier A3 and the resistor network consisting of RFB, RG1, and RG2. A3 operates as a modified summing amplifier, where the DAC controls the noninverting input and the inverting input has one path to GND and a second to VREF. This configuration allows the single-ended DAC to create both the unipolar 0-V to 5-V and 0-V to 10-V outputs and the bipolar ±5-V and ±10-V outputs by modifying the values of RG1 and RG2.

Figure 96 generates clean ±15-V supplies using a synchronous step-down regulator (TPS54062) and two high-voltage, ultra-low noise, linear regulators (TPS7A49 and TPS7A30). A field supply terminal is shown instead of the more common use case of a back-plane supply. The design uses two triple channel isolators (ISO7631FC) to provide galvanic isolation for the digital lines to communicate to the main controller. Note that these isolators can be driven by the internally-generated supply (DVDD) from the DACx760 to save components and cost. The DACx760 supplies up to 10 mA that meets the supply requirements of the two isolators running at up to 10 Mbps. Note that additional cost savings are possible if noncritical digital signals such as CLR and ALARM are tied to GND or left unconnected. Finally, a protection scheme with transient voltage suppressors and other components is placed on all pins which connect to the field.

The protection circuitry is designed to provide immunity to the IEC61000-4 test suite which includes system-level industrial transient tests. The protection circuit includes transient voltage suppressor (TVS) diodes, clamp-to-rail steering diodes, and pass elements in the form of resistors and ferrite beads. For more detail about selecting these components, see TIPD153.

Application Curves

The current output circuit was measured in 0-mA to 24-mA mode using an 8.5 digit digital multi-meter to measure the output while driving a 300-Ω load at 25°C. The measured results are shown in Figure 98. The voltage output circuit was measured in ±10-V mode using an 8.5 digit digital multi-meter to measure the output while driving a
1-kΩ load at 25°C. The measured results are shown in Figure 99. In both cases, the voltage and current outputs remain within the specified performance of the data sheet.

The design was also exposed to IEC61000-4 electrostatic discharge, electrically fast transient, conducted immunity, and radiated immunity tests on both the current and voltage outputs. During each of these tests a 6.5 digit digital multi-meter, set in fast 5.5 digit acquisition mode, was used to monitor the outputs. Complete data sets for the voltage and current outputs during these tests are available in TIPD153.

DAC7760 DAC8760 D001_SBAS528B.gif
Figure 98. Voltage Output TUE Versus Code
DAC7760 DAC8760 D002_SBAS528B.gif
Figure 99. Current Output TUE Versus Code