The DAC8760 and DAC7760 are low-cost, precision, fully-integrated, 16-bit an 12-bit digital-to-analog converters (DACs) designed to meet the requirements of industrial process control applications. These devices can be programmed as a current output with a range of 4 mA to 20 mA, 0 mA to 20 mA, or 0 mA to 24 mA; or as a voltage output with a range of 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V, with a 10% overrange (0 V to 5.5 V, 0 V to 11 V, ±5.5 V, or ±11 V). Both current and voltage outputs can be simultaneously enabled while being controlled by a single data register.
These devices include a power-on-reset function to ensure powering up in a known state (both IOUT and VOUT are disabled and in a high-impedance state). The CLR and CLR-SEL pins set the voltage outputs to zero-scale or mid-scale, and the current output to the low-end of the range, if the output is enabled. Zero code error and gain error calibration registers can be programmed to digitally calibrate the device in the end system. The output slew rate is also programmable. These devices can AC couple an external HART signal on the current output and can operate with either a single 10-V to 36-V supply, or dual supplies up to ±18 V.
The DAC8760 and DAC7760 (DACx760) consist of a resistor-string digital-to-analog converter (DAC) followed by a buffer amplifier. The output of the buffer drives the current output and the voltage output. The resistor-string section is simply a string of resistors, each of value R, from REF to GND, as Figure 82 illustrates. This type of architecture makes sure the DAC is monotonic. The 16-bit binary digital code (DAC8760) loaded to the DAC register determines at which node on the string the voltage is tapped off before it is fed into the output amplifier.
The current-output stage converts the voltage output from the string to current. The voltage output provides a buffered output of the programmed range to the external load. When the current output or the voltage output is disabled, it is in a high impedance (Hi-Z) state. After power-on, both output stages are disabled. See Controlling the VOUT and IOUT Pins for different options to configure the current and voltage output pins.
The voltage output stage as conceptualized in Figure 83 provides the voltage output according to the DAC code and the output range setting. The output range can be programmed as 0 V to 5 V or 0 V to 10 V for unipolar output mode, and ±5 V or ±10 V for bipolar output mode. In addition, an option is available to increase the output voltage range by 10%. The output current drive can be up to 10 mA. The output stage has short-circuit current protection that limits the output current to 30 mA. To maintain proper performance, a minimum 0.5-V power-supply headroom is required. The voltage output is able to drive a capacitive load up to 1 µF. For loads greater than 20 nF, an external compensation capacitor can be connected between CMP and VOUT to keep the output voltage stable at the expense of reduced bandwidth and increased settling time.
The +VSENSE pin is provided to enable sensing of the load by connecting to points electrically closer to the load. This configuration allows the internal output amplifier to make sure that the correct voltage is applied across the load, as long as headroom is available on the power supply. Ideally, this pin is used to correct for resistive drops on the system board and is connected to VOUT at the terminals. In some cases, both VOUT and +VSENSE are brought out as terminals and, through separate lines, connected remotely together at the load. In such cases, if the +VSENSE line is cut, the amplifier loop is broken; use an optional 5-kΩ resistor between VOUT and +VSENSE to prevent this from occurring. The –VSENSE pin, on the other hand, is provided as a GND sense reference output from the internal VOUT amplifier. The output swing of the VOUT amplifier is relative to the voltage seen at this pin. The actual voltage difference between the –VSENSE pin and the device GND pins is not expected to be more than a few 100 µV. The internal resistor in Figure 83 between the device internal GND and the –VSENSE pin is typically 2 kΩ.
After power on, the power-on-reset circuit makes sure that all registers are at their default values. Therefore, the voltage output buffer is in a Hi-Z state; however, the +VSENSE pin connects to the amplifier inputs through an internal 60-kΩ feedback resistor (RFB in Figure 83). If the VOUT and +VSENSE pins are connected together, the VOUT pin is also connected to the same node through the feedback resistor. This node is protected by internal circuitry and settles to a value between GND and the reference input.
For unipolar output mode:
For bipolar output mode:
|0 V to 5 V||1|
|0 V to 10 V||2|
The voltage range is set according to the value of the RANGE bits and the OVR bit in the Control Register. The OVR bit makes the gain value in Table 1 increase by 10%, thereby increasing the voltage output range, as shown in Table 10 (see Setting Voltage and Current Output Ranges for more details).
The current output stage consists of a preconditioner and a current source as conceptualized in Figure 84. This stage provides a current output according to the DAC code. The output range can be programmed as 0 mA to
20 mA, 0 mA to 24 mA, or 4 mA to 20 mA. An external boost transistor can be used to reduce the power dissipation of the device. The maximum compliance voltage on pin IOUT equals (AVDD – 2 V). In single power-supply mode, the maximum AVDD is 36 V, and the maximum compliance voltage is 34 V. After power on, the IOUT pin is in a Hi-Z state.
Resistor RSET (used to convert the DAC voltage to current) determines the stability of the output current over temperature. If desired, an external, low-drift, precision 15-kΩ resistor can be connected to the ISET-R pin and used instead of the internal RSET resistor.
For a 0-mA to 20-mA output range:
For a 0-mA to 24-mA output range:
For a 4-mA to 20-mA output range:
The current-output range is normally set according to the value of the RANGE bits in the Control Register. When both the voltage and current outputs are enabled in dual-output mode, the range is set by the IOUT RANGE bits in the Configuration Register. See Setting Voltage and Current Output Ranges for more details. For more details on controlling the current output when both the VOUT and IOUT pins are simultaneously enabled, see Controlling the VOUT and IOUT Pins.
The DACx760 includes an integrated 5-V reference with a buffered output (REFOUT) capable of driving up to
5 mA (source or sink) with an initial accuracy of ±5 mV (maximum) and a temperature drift coefficient of 10 ppm/°C (maximum).
An internally generated 4.6-V supply capable of driving up to 10 mA can be output on DVDD by leaving the DVD-EN pin unconnected. This supply eases the system power supply design especially when an isolation barrier is required to cross and generate the digital supply. It can be used to drive isolation components used for the digital data lines and other miscellaneous components like references and temp sensors. See Figure 96 for an example application. If an external supply is preferred, the DVDD pin (which can be driven up to 5.5 V in this case) can be made into an input by tying DVDD-EN to GND (see Electrical Characteristics for detailed specifications).
The DAC has an asynchronous clear function through the CLR pin, which is active-high and allows the voltage output to be cleared to either zero-scale code or midscale code. This action is user-selectable through the CLR-SEL pin or the CLRSEL bit of Table 19, as Table 2 describes. The CLR-SEL pin and CLRSEL register are ORed together. The current output clears to the bottom of its preprogrammed range. When the CLR signal returns to low, the output remains at the cleared value. The pre-clear value can be restored by pulsing the LATCH signal without clocking any data. A new value cannot be programmed until the CLR pin returns to low. Note that in dual-output mode, the value that the DAC data register is cleared to follows the settings for the voltage output mode.
|UNIPOLAR OUTPUT RANGE||BIPOLAR OUTPUT RANGE|
|0||0 V||0 V|
In addition to defining the output value for a clear operation, the CLRSEL bit and the CLR-SEL pin also define the default output value. During the selection of a new voltage range, the output value corresponds to the definitions given in Table 9. To avoid glitches on the output, disable the output by writing a 0 to the OUTEN bit of the Table 19 before changing the voltage range. When the OUTEN bit is set to 1, the output goes to the default value as defined by the CLRSEL bit and the CLR-SEL pin.
The DACx760 has internal power on reset (POR) circuitry for both the digital DVDD and analog AVDD supplies. This circuitry makes sure that the internal logic and power-on state of the DAC power up to the proper state independent of the supply sequence. The recommended power-supply sequence is to first have the analog AVDD supply come up, followed by the digital supply DVDD. DVDD can also come up first as long as AVDD ramps to at least 5 V within 50 µs. If neither of these conditions can be satisfied, TI recommends that a software reset command be issued via the SPI bus after both AVDD and DVDD are stable.
The DACx760 incorporates two internal POR circuits for the DVDD and AVDD supplies. The DVDD and AVDD POR signals are ANDed together so that both supplies must be at their minimal specified values for the device to not be in a reset condition. These POR circuits initialize internal logic and registers as well as set the analog outputs to a known state while the device supplies are ramping. All registers are reset to their default values with the default value of the data register being determined by the CLR-SEL pin. The behavior of IOUT and VOUT is described in their respective sections. Typically the POR function can be ignored as long as the device supplies power up and maintain the specified minimum voltage levels. However, in the case of supply drop or brownout, the DACx760 can have an internal POR reset event or lose digital memory integrity. Figure 85 represents the threshold levels for the internal POR for both the DVDD and AVDD supplies.
For the DVDD supply, no internal POR occurs for nominal supply operation from 2.7 V (supply minimum) to 5.5 V (supply maximum). For the DVDD supply region between 2.4 V (undefined operation threshold) and 0.8 V (POR threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For the DVDD supply below 0.8 V (POR threshold), the internal POR resets as long as the supply voltage is below 0.8 V for approximately 1 ms.
For the AVDD supply, no internal POR occurs for nominal supply operation from 10 V (supply minimum) to 36 V (supply maximum). For AVDD supply voltages between 8 V (undefined operation threshold) to 1 V (POR threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For the AVDD supply below 1 V (POR threshold), the internal POR resets as long as the supply voltage is below 1 V for approximately 1 ms. In case the DVDD or AVDD supply drops to a level where the internal POR signal is indeterminate, either power cycle the device or toggle the LATCH pin followed by a software reset. Both options initialize the internal circuitry to a known state and provide proper operation.
The device also provides an alarm detection feature. When one or more of following events occur, the ALARM pin goes low:
When the ALARM pins of multiple DACx760 devices are connected together to form a wired-AND function, the host processor must read the status register of each device to know all the fault conditions that are present. Note that the thermal alarm has hysteresis of about 18°C. After being set, the alarm only resets when the die temperature drops below 124°C.
This feature is useful to make sure that communication between the host processor and the DACx760 has not been lost. It can be enabled by setting the WDEN bit of the Configuration Register to 1. The watchdog timeout period can be set using the WDPD bits of the configuration register; see Table 3. The timer period is based off an internal oscillator with a typical value of 8 MHz.
|WDPD BITS||WATCHDOG TIMEOUT PERIOD (Typical, ms)|
If enabled, the chip must have an SPI frame with 0x95 as the write address byte written to the device within the programmed timeout period. Otherwise, the ALARM pin asserts low and the WD-FLT bit of the status register is set to 1. Note that the ALARM pin can be asserted low for any of the different conditions as explained in the Alarm Detection section. The WD-FLT bit is reset to 0 with a software reset, or by disabling the watchdog timer, or by powering down the device.
When using multiple DACx760 devices in a daisy-chain configuration, the open-drain ALARM pins of all devices can be connected together in a wired-AND function. The watchdog timer can be enabled in any number of the devices in the chain although enabling it in one device is sufficient. The wired-AND ALARM pin may get pulled low because of the simultaneous presence of different trigger conditions in the daisy-chained devices. The host processor must read the status register of each device to know all the fault conditions present in the chain.
As explained in the Serial Peripheral Interface (SPI) section of this document, the DACx760 digital interface constantly clocks in data regardless of the status of the LATCH pin, and data are unconditionally latched on the rising edge of the LATCH pin. A rising edge on the LATCH pin is the only way the device takes action on clocked data.
The watchdog timer can also be enabled without a rising edge on the LATCH pin if a specific pattern, see Table 4, is present on DIN and SCLK. When this pattern enables the watchdog timer, this enabled status is not reflected in the configuration register. During this condition, the watchdog timer cannot be enabled or disabled through writes to the configuration register. Additionally, the alarm condition can only be cleared through a power-on reset event triggered either by a reset command or cycling power to the device. The ALARM pin also indicates that the watchdog timer has triggered.
|BIT FORMAT||BIT SETTING|
|Hex||D15 = 1||X|
|Hex||X||DB2 = 1|
If the watchdog timer feature is enabled as described in the Watchdog Timer section along with full compliance of the watchdog timer, then the pattern provided in Table 4 on DIN and SCLK does not have any effect.
If the DACx760 is used in a noisy environment, error checking can be used to check the integrity of SPI data communication between the device and the host processor. This feature can be enabled by setting the CRCEN bit of the Configuration Register to 1. The frame error checking scheme is based on the CRC-8-ATM (HEC) polynomial x8 + x2 + x + 1 (that is, 100000111). When error checking is enabled, the SPI frame width is 32 bits, as shown in Table 5. Start with the default 24-bit frame and enable frame error checking through the CRCEN bit and switch to the 32-bit frame. The normal 24-bit SPI data are appended with an 8-bit CRC polynomial by the host processor before feeding it to the device. For a register readback, the CRC polynomial is output on the SDO pins by the device as part of the 32-bit frame.
|BIT 31:BIT 8||BIT 7:BIT 0|
|Normal SPI frame data||8-bit CRC polynomial|
When in CRC mode the DACx760 calculates CRC words every 32-clocks, unconditional of when the LATCH pin toggles. The DACx760 decodes the 32-bit input frame data to compute the CRC remainder. If no error exists in the frame, the CRC remainder is zero. When the remainder is non-zero (that is, the input frame has single- or multiple-bit errors), the ALARM pin asserts low and the CRC-FLT bit of the status register is also set to 1. Note that the ALARM pin can be asserted low for any of the different conditions as explained in Alarm Detection. The CRC-FLT bit is reset to 0 with a software reset, or by disabling the frame error checking, or by powering down the device. In the case of a CRC error, the specific SPI frame is blocked from writing to the device.
Frame error checking can be enabled for any number of DACx760 devices connected in a daisy-chain configuration. However, TI recommends enabling error checking for none or all devices in the chain. When connecting the ALARM pins of all combined devices, forming a wired-AND function, the host processor must read the status register of each device to know all the fault conditions present in the chain. For proper operation, the host processor must provide the correct number of SCLK cycles in each frame, taking care to identify whether or not error checking is enabled in each device in the daisy-chain.
If the CRC mode is enabled on the first frame issued to the device after power-up, TI suggests that a no operation, or NOOP, command is issued to the device in order to reset the SPI clock and SPI frame alignment in the event that any transients on the SCLK line are interpreted as SCLK periods. A NOOP command can be issued to the device by simply toggling the LATCH pin without any SCLK periods.
This section is only applicable for applications where the DACx760 is digitally interfaced via an SPI bus that has other devices on the bus that are not DACx760 devices, and there are multiple DACx760s in a daisy-chain configuration.
As explained in the SPI Shift Register section of this document, the DACx760 digital interface constantly clocks in data regardless of the status of the LATCH pin, and data are unconditionally latched on the rising edge of the LATCH pin. A rising edge on the LATCH pin is the only way the device takes action on clocked data.
The frame error checking (CRC) mode can also be enabled without a rising edge on the LATCH pin if a specific pattern, shown in Table 6, is present on DIN and SCLK. When this pattern enables CRC mode, this enabled status is not reflected in the configuration register. During this condition, the CRC mode cannot be enabled or disabled through writes to the configuration register. Additionally, the alarm pin and status registers does not indicate CRC alarm conditions, and frames with incorrect or missing CRC bits are not disregarded as described in the Frame Error Checking section. During this condition the devices in daisy-chain output data on the SDO pin on a 32-bit frame structure instead of 24-bits. The CRC mode can only be cleared through a power-on reset event triggered either by a reset command or cycling power to the device.
|BIT FORMAT||BIT SETTING|
|Hex||X||DB2 = 1|
If the CRC feature is enabled as described in the Frame Error Checking section along with full compliance of the frame error checking, then the pattern provided in Table 6 on DIN and SCLK does not have any effect.
The device implements a user-calibration function to allow for trimming the system gain and zero errors. There is a gain calibration register and a zero calibration register; the DAC output is calibrated according to the value of these registers. The range of gain adjustment is typically ±50% of full-scale with 1 LSB per step. The gain register must be programmed to a value of 0x8000 to achieve the default gain of 1 because the power-on value of the register is 0x0000, which is equivalent to a gain of 0.5. The zero code adjustment is typically ±32,768 LSBs with 1 LSB per step. The input data format of the gain register is unsigned straight binary, and the input data format of the zero register is twos complement. The gain and offset calibration is described by Equation 6.
This is a purely digital implementation and the output is still limited by the programmed value at both ends of the voltage or current output range. In addition, remember that the correction only makes sense for endpoints inside of the true device end points. To correct more than just the actual device error, for example a system offset, the valid range for the adjustment changes accordingly and must be taken into account. This range is set by the RANGE, OVR, DUAL OUTEN, and IOUT RANGE bits, as described in Setting Voltage and Current Output Ranges.
New calibration codes are only applied to subsequent writes of the DAC data register. Updating the calibration codes does not automatically update the DAC output. Additionally, TI recommends configuring the calibration codes along with the slew rate control prior to applying new DAC data.
The slew rate control feature controls the rate at which the output voltage or current changes. With the slew rate control feature disabled, the output changes smoothly at a rate limited by the output drive circuitry and the attached load.
To reduce the slew rate, enable the slew rate control feature through bit 4 of the Table 19. With this feature enabled, the output does not slew directly between the two values. Instead, the output steps digitally at a rate defined by bits [7:5] (SRSTEP) and bits [11:8] (SRCLK) of the control register. SRCLK defines the rate at which the digital slew updates; SRSTEP defines the amount by which the output value changes at each update. If the DAC data register is read while the DAC output is still changing, the instantaneous value is read. Table 7 lists the slew rate step-size options. Table 8 summarizes the slew rate update clock options.
|SRSTEP||STEP SIZE (LSB)|
|SRCLK||DAC UPDATE FREQUENCY (Hz)|
The time required for the output to slew over a given range can be expressed as Equation 7:
When the slew rate control feature is enabled, all output changes happen at the programmed slew rate. This configuration results in a staircase formation at the output. If the CLR pin is asserted, the output slews to the zero-scale value at the programmed slew rate. Bit 1 (SR-ON) of the Status Register can be read to verify that the slew operation has completed. The update clock frequency for any given value is the same for all output ranges. The step size, however, varies across output ranges for a given value of step size because the LSB size is different for each output range. Figure 86 illustrates an example of IOUT slewing at a rate set by the previously described parameters. In this example for the DAC8760 (LSB size of 305 nA for the 0-mA to 20-mA range), the settings correspond to an update clock frequency of 6.9 kHz and a step size of 128 LSB. As can be seen for the case with no capacitors on CAP1 or CAP2, the steps occur at the update clock frequency (6.9 kHz corresponds to a period close to 150 µs) and the size of each step is about 38 µA (128 × 305 nA). The slew time for a specific code change can be calculated using Equation 7.
Apply the desired programmable slew rate control setting prior to updating the DAC data register because updates to the DAC data register in tandem with updates to the slew rate control registers can create race conditions that may result in unexpected DAC data.
For voltage and current outputs in normal mode (VOUT and IOUT are not simultaneously enabled), the output range is set according to Table 9.
|000||0 V to +5 V|
|001||0 V to +10 V|
|101||4 mA to 20 mA|
|110||0 mA to 20 mA|
|111||0 mA to 24 mA|
Note that changing the RANGE bits at any time causes the DAC data register to be cleared based on the value of CLR-SEL (pin or register bit) and the new value of the RANGE bits.
In addition to the RANGE bits, the OVR bit extends the voltage output range by 10%. if the OVR bit is set, the voltage output range follows Table 10, as long as there is headroom with the supply.
|VOLTAGE OUTPUT RANGE||VOLTAGE OUTPUT OVERRANGE|
|0 V to 5 V||0 V to 5.5 V|
|0 V to 10 V||0 V to +11 V|
|±5 V||±5.5 V|
|±10 V||±11 V|
When VOUT and IOUT are simultaneously enabled (dual-output mode) by setting the DUAL OUTEN bit in the Configuration Register, the voltage output is controlled by the RANGE bits in the Control Register (see Table 11), and the current output is controlled by the IOUT RANGE bits in the Configuration Register (see Table 12).
|000||0 V to +5 V|
|001||0 V to +10 V|
|01||4 mA to 20 mA|
|10||0 mA to 20 mA|
|11||0 mA to 24 mA|
An external NPN transistor can be used as shown in Figure 87 to reduce power dissipation on the die. Most of the load current flows through the NPN transistor with a small amount flowing through the on-chip PMOS transistor based on the gain of the NPN transistor. This reduces the temperature induced drift on the die and internal reference and is an option for use cases at the extreme end of the supply, load current, and ambient temperature ranges. Resistor R2 stabilizes this circuit for cases where the RLOAD is a short or a very small load like a multimeter. Recommended values for R1, R2 and C1 in this circuit are 1 kΩ, 20 Ω and 0.22 µF. An equivalent solution is to place R2 (with a recommended value of 2 kΩ instead of the 20 Ω) in series with the base of the transistor instead of the configuration shown in Figure 87. Note that there is some gain error introduced by this configuration as seen in Figure 47 for the 0-mA to 24-mA range. TI recommends using the internal transistor in most cases as the values in the Electrical Characteristics are based on the configuration with the internal on-chip PMOS transitor.
The VQFN package provides access to internal nodes of the circuit as shown in Figure 93. Capacitors can be placed on these pins and AVDD to form a filter on the output current, reducing bandwidth and the slew rate of the output. However, to achieve large reductions in slew rate, the programmable slew rate can be used to avoid having to use large capacitors. Even in that case, the capacitors on CAP1 and CAP2 can be used to smooth out the stairsteps caused by the digital code changes as shown in Figure 88. However, note that power supply ripple also couples into the part through these capacitors.
On the DACx760, HART digital communication can be modulated onto the input signal by two methods:
This method is limited to the case where the RANGE bits of the Table 19 are programmed to the 4-mA to 20-mA range. Some applications require going beyond the 4-mA to 20-mA range. In those cases, see second method described in this section.
The external HART signal (ac voltage; 500 mVPP, 1200 Hz and 2200 Hz) can be capacitively coupled in through the HART-IN pin and transferred to a current that is superimposed on the 4-mA to 20-mA current output. The HART-IN pin has a typical input impedance of 35 kΩ that together with the input capacitor used to couple the external HART signal forms a filter to attenuate frequencies beyond the HART band-pass region. In addition to this filter, an external passive filter is recommended to complete the filtering requirements of the HART specifications. Figure 89 illustrates the output current versus time operation for a typical HART signal.
NOTE:DC current = 6 mA.
Table 13 specifies the performance of the HART-IN pin.
|Input impedance||HART signal ac-coupled into pin||35||kΩ|
|Output current (peak-to-peak)||Input signal of 500 mV (peak-to-peak)||0.9||1||1.1||mA|
The device is controlled over a versatile four-wire serial interface (SDI, SDO, SCLK, and LATCH) that operates at clock rates of up to 30 MHz and is compatible with SPI, QSPI™, Microwire, and digital signal processing (DSP) standards. The SPI communication command consists of a write address byte and a data word for a total of 24 bits. The timing for the digital interface is shown in Figure 1, Figure 2, and Figure 3.
The default frame is 24 bits wide (refer to the Frame Error Checking section for 32-bit frame mode) and begins with the rising edge of SCLK that clocks in the MSB. The subsequent bits are latched on successive rising edges of SCLK. The default 24-bit input frame consists of an 8-bit address byte followed by a 16-bit data word as shown in Table 14.
|BIT 23:BIT 16||BIT 15:BIT 0|
|Address byte||Data word|
The host processor must issue 24 bits before it issues a rising edge on the LATCH pin. Input data bits are clocked in regardless of the LATCH pin and are unconditionally latched on the rising edge of LATCH. By default, the SPI shift register resets to 000000h at power on or after a reset.
|0x00||No operation (NOP)|
|0x01||Write DAC Data register|
|0x55||Write control register|
|0x56||Write reset register|
|0x57||Write configuration register|
|0x58||Write DAC gain calibration register|
|0x59||Write DAC zero calibration register|
|0x95||Watchdog timer reset|
A read operation is accomplished when the address byte is 0x02. Follow the read operation with a no-operation (NOP) command to clock out an addressed register, as shown in Figure 2. To read from a register, the address byte and data word is as shown in Table 16. The read register value is output MSB first on SDO on successive falling edges of SCLK.
|ADDRESS BYTE||DATA WORD|
|BIT 15:BIT 6||BIT 5:BIT 0|
|0x02||X (don't care)||Register read address (see Table 17)|
Table 17 shows the register read addresses available on the DACx760 devices.
|XX XX00||Read status register|
|XX XX01||Read DAC data register|
|XX XX10||Read control register|
|00 1011||Read configuration register|
|01 0011||Read DAC gain calibration register|
|01 0111||Read DAC zero calibration register|
SCLK can operate in either continuous or burst mode as long as the LATCH rising edge occurs after the appropriate number of SCLK cycles. Providing more than or less than 24 SCLK cycles before the rising edge of LATCH results in incorrect data being programmed into the device registers and incorrect data sent out on SDO. The rising edge of SCLK that clocks in the MSB of the 24-bit input frame marks the beginning of the write cycle, and data are written to the addressed registers on the rising edge of LATCH.
For systems that contain multiple DACx760s, use the SDO pin to daisy-chain several devices. This mode is useful in reducing the number of serial interface lines in applications that use multiple SPI devices. Daisy-chain mode is enabled by setting the DCEN bit of the control register to 1. By connecting the SDO of the first device to the SDI input of the next device in the chain, a multiple-device interface is constructed, as Figure 90 illustrates.
Like stand-alone operation, the SPI daisy-chain write operation requires one frame, and the read requires two frames. The rising edge of SCLK that clocks in the MSB of the input frame marks the beginning of the write cycle. When the serial transfer to all devices is complete, LATCH is taken high. This action transfers the data from the SPI shift registers to the device internal register of each DACx760 in the daisy-chain. However, the number of clocks in each frame in this case depends on the number of devices in the daisy chain. For two devices, each frame is 48 clocks; the first 24 clocks are for the second DAC and the next 24 bits are for the first DAC. For a readback, the data are read from the two DACs in the following 48-bit frame; the first 24 clocks are for the second DAC and the next 24 clocks are for the first DAC. The input data to the DACs during the second frame can be another command or NOP. Similar to the two-device case described, for N devices, each frame is N × 24 clocks, where N is the total number of DACx760s in the chain.
The serial clock can be a continuous or gated clock. A continuous SCLK source can only be used if LATCH is taken high after the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used and LATCH must be taken high after the final clock to latch the data.
Table 18 shows the available commands and registers on the DACx760 devices. No operation, read operation, and watchdog timer refer to commands and are not explicit registers. For more information on these commands, see Read Operation and Watchdog Timer. See DACx760 Register Descriptions for descriptions of all DACx760 registers.
|DATA BITS (DB15:DB0)|
|Configuration||R/W||X(1)||IOUT RANGE||DUAL OUTEN||APD||Reserved||CALEN||HARTEN||CRCEN||WDEN||WDPD|
|DAC Data (2)||R/W||D15:D0|
|Read Operation (3)||—||X||READ ADDRESS|
|DAC Gain Calibration (2)||RW||G15:G0, unsigned|
|DAC Zero Calibration (2)||RW||Z15:Z0, signed|
|Watchdog Timer (3)||—||X|
The DACx760 control register is written to at address 0x55. Table 19 shows the description for the control register bits.
|DB15||CLRSEL||0||VOUT clear value select bit.
When bit = 0, VOUT is 0 V in DAC Clear mode or after reset.
When bit = 1, VOUT is midscale in unipolar output and negative-full-scale in bipolar output in DAC Clear mode or after reset.
|DB14||OVR||0||Setting the bit increases the voltage output range by 10%.|
|DB13||REXT||0||External current setting resistor enable.|
Bit = 1: Output is determined by RANGE bits.
Bit = 0: Output is disabled. IOUT and VOUT are Hi-Z.
|DB11:DB8||SRCLK[3:0]||0000||Slew rate clock control. Ignored when bit SREN = 0|
|DB7:DB5||SRSTEP[2:0]||000||Slew rate step size control. Ignored when bit SREN = 0|
|DB4||SREN||0||Slew Rate Enable.
Bit = 1: Slew rate control is enabled, and the ramp speed of the output change is determined by SRCLK and SRSTEP.
Bit = 0: Slew rate control is disabled. Bits SRCLK and SRSTEP are ignored. The output changes to the new level immediately.
|DB2:DB0||RANGE[2:0]||000||Output range bits.|
The DACx760 configuration register is written to at address 0x57. Table 20 summarizes the description for the configuration register bits.
|DB15:DB11||0h||Reserved. User must not write any value other than zero to these bits.|
|DB10:DB9||IOUT RANGE||00||IOUT range. These bits are only used if both voltage and current outputs are simultaneously enabled through bit 8 (DUAL OUTEN). The voltage output range is still controlled by bits 2:0 of the Control Register (RANGE bits). The current range is controlled by these bits and has similar behavior to RANGE[1:0] when RANGE = 1. However, unlike the RANGE bits, a change to this field does not make the DAC data register go to its default value.|
|DB8||DUAL OUTEN||0||DAC dual output enable. This bit controls if the voltage and current outputs are enabled simultaneously. Both are enabled when this bit is high. However, both outputs are controlled by the same DAC data register.|
|DB7||APD||0||Alternate power down. On power-up, +VSENSE is connected to the internal VOUT amplifier inverting terminal. Diodes exist at this node to REFIN and GND. Setting this bit connects this node to ground through a resistor. When set, the equivalent resistance seen from +VSENSE to GND is 70 kΩ. This is useful in applications where the VOUT and IOUT terminals are tied together.|
|DB6||0||Reserved. Do not write any value other than zero to these bits.|
|DB5||CALEN||0||User calibration enable. When user calibration is enabled, the DAC data are adjusted according to the contents of the gain and zero calibration registers. See User Calibration.|
|DB4||HARTEN||0||Enable interface through HART-IN pin (only valid for IOUT set to 4-mA to 20-mA range through RANGE bits).
Bit = 1: HART signal is connected through internal resistor and modulates output current.
Bit = 0: HART interface is disabled.
|DB3||CRCEN||0||Enable frame error checking.|
|DB2||WDEN||0||Watchdog timer enable.|
|DB1:DB0||WDPD[1:0]||00||Watchdog timeout period.|
The DAC registers consist of a DAC data register (Table 21), a DAC gain calibration register (Table 22), and a DAC zero calibration register (Table 23). User calibration as described in User Calibration is a feature that allows for trimming the system gain and zero errors. Table 21 through Table 23 show the DAC8760, 16-bit version of these registers. The DAC7760 (12-bit version) register contents are located in DB15:DB4. For DAC7760, DB3:DB0 are don't care bits when writing and zeros when reading.
|DB15:DB0||D15:D0||0000h||DAC data register. Format is unsigned straight binary.|
|DB15:DB0||G15:G0||0000h||Voltage and current gain calibration register for user calibration. Format is unsigned straight binary.|
|DB15:DB0||Z15:Z0||0000h||Voltage and current zero calibration register for user calibration. Format is twos complement.|
The DACx760 reset register is written to at address 0x56. Table 24 provides the description.
|DB15:DB1||0000h||Reserved. Writing to these bits does not cause any change.|
|DB0||RESET||0||Software reset bit. Writing 1 to the bit performs a software reset to reset all registers and the ALARM status to the respective power-on reset default value. After reset completes the RESET bit clears itself.|
This read-only register consists of four ALARM status bits (CRC-FLT, WD-FLT, I-FLT, and T-FLT) and bit SR-ON that shows the slew rate status.
The device continuously monitors the output and die temperature. When an alarm occurs, the corresponding ALARM status bit is set (1). Whenever an ALARM status bit is set, it remains set until the event that caused it is resolved. The ALARM bit can only be cleared by performing a software reset, or a power-on reset (by cycling power), or having the error condition resolved. These bits are reasserted if the ALARM condition continues to exist in the next monitoring cycle.
The ALARM bit goes to 0 when the error condition is resolved.
|DB15:DB5||000h||Reserved. Reading these bits returns 0.|
|DB4||CRC-FLT||0||Bit = 1 indicates CRC error on SPI frame.
Bit = 0 indicates normal operation.
|DB3||WD-FLT||0||Bit = 1 indicates watchdog timer timeout.
Bit = 0 indicates normal operation.
|DB2||I-FLT||0||Bit = 1 indicates Open Circuit or Compliance Voltage Violation in IOUT loading.
Bit = 0 indicates IOUT load is at normal condition.
|DB1||SR-ON||0||Bit = 1 when DAC code is slewing as determined by SRCLK and SRSTEP.
Bit = 0 when DAC code is not slewing.
|DB0||T-FLT||0||Bit = 1 indicates die temperature is over 142°C.
Bit = 0 indicates die temperature is not over 142°C.