SBAS528C June   2013  – January 2018 DAC7760 , DAC8760


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: AC
    7. 7.7  Timing Requirements: Write Mode
    8. 7.8  Timing Requirements: Readback Mode
    9. 7.9  Timing Requirements: Daisy-Chain Mode
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  DAC Architecture
      2. 8.3.2  Voltage Output Stage
      3. 8.3.3  Current Output Stage
      4. 8.3.4  Internal Reference
      5. 8.3.5  Digital Power Supply
      6. 8.3.6  DAC Clear
      7. 8.3.7  Power-Supply Sequence
      8. 8.3.8  Power-On Reset
      9. 8.3.9  Alarm Detection
      10. 8.3.10 Watchdog Timer
        1. The DACx760 Shares the SPI Bus With Other Devices (Non-DACx760)
      11. 8.3.11 Frame Error Checking
        1. The DACx760 Shares the SPI Bus With Other Devices (Non-DACx760)
      12. 8.3.12 User Calibration
      13. 8.3.13 Programmable Slew Rate
    4. 8.4 Device Functional Modes
      1. 8.4.1 Setting Voltage and Current Output Ranges
      2. 8.4.2 Boost Configuration for IOUT
      3. 8.4.3 Filtering the Current Output (only on the VQFN package)
      4. 8.4.4 HART Interface
        1. For 4-mA to 20-mA Mode
        2. For All Current Output Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI)
        1. SPI Shift Register
        2. Write Operation
        3. Read Operation
        4. Stand-Alone Operation
        5. Daisy-Chain Operation
    6. 8.6 Register Maps
      1. 8.6.1 DACx760 Commands and Register Map
        1. DACx760 Register Descriptions
          1. Control Register
          2. Configuration Register
          3. DAC Registers
          4. Reset Register
          5. Status Register
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Controlling the VOUT and IOUT Pins
        1. VOUT and IOUT Pins are Independent Outputs, Never Simultaneously Enabled
        2. VOUT and IOUT Pins are Independent Outputs, Simultaneously Enabled
        3. VOUT and IOUT Pins are Tied Together, Never Simultaneously Enabled
      2. 9.1.2 Implementing HART in All Current Output Modes
        1. Using CAP2 Pin on VQFN Package
        2. Using the ISET-R Pin
      3. 9.1.3 Short-Circuit Current Limiting
    2. 9.2 Typical Application
      1. 9.2.1 Voltage and Current Output Driver for Factory Automation and Control, EMC and EMI Protected
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and Functions

RHA Package
40-Pin VQFN
Top View
PWP Package
Top View
Thermal pad connected to AVSS

Pin Functions

ALARM 2 3 Digital output Alarm pin. Open drain output. External pullup resistor required (10 kΩ). The pin goes low (active) when the ALARM condition is detected (open circuit, over temperature, timeout and so forth).
AVDD 36 24 Supply input Positive analog power supply.
AVSS 14, 37 1 Supply input Negative analog power supply in dual power-supply operation. Connects to GND in single power-supply operation.
BOOST 27 20 Analog output Boost pin. External transistor connection (optional).
CAP1 28 Analog input Connection for current output filtering capacitor (optional).
CAP2 29 Analog input Connection for current output filtering capacitor (optional).
CLR 5 6 Digital input Clear input. Logic high on this pin causes the part to enter CLEAR state. Active high.
CLR-SEL 4 5 Digital input Selects the VOUT value in CLEAR state, after power-on and reset.
CMP 24 17 Analog output External compensation capacitor connection pin (optional). Addition of the external capacitor (connected between VOUT and this pin) improves the stability with high capacitive loads at the VOUT pin by reducing the bandwidth of the output amplifier, thus increasing the settling time.
DIN 8 9 Digital input Serial data input. Data are clocked into the 24-bit input shift register on the rising edge of the serial clock input. Schmitt-Trigger logic input.
DVDD 39 2 Supply input or output Digital power supply. Can be input or output, depending on DVDD-EN pin.
DVDD-EN 23 16 Digital input Internal power-supply enable pin. Connect this pin to GND to disable the internal supply, or leave this pin unconnected to enable the internal supply. When this pin is connected to GND, an external supply must be connected to the DVDD pin.
GND 3, 4 Supply input Ground reference point for all digital circuitry of the device. Connect to 0 V.
GND 12, 13, 15 11, 12 Supply input Ground reference point for all analog circuitry of the device. Connect to 0 V.
HART-IN 25 18 Analog input Input pin for HART modulation.
IOUT 26 19 Analog output Current output pin
ISET-R 16 13 Analog input Connection pin for external precision resistor (15 kΩ). See the Detailed Description section of this data sheet.
LATCH 6 7 Digital input Load DAC registers input. A rising edge on this pin loads the input shift register data into the DAC data and control registers and updates the DAC outputs.
NC 1, 10, 11, 19, 20, 21, 22, 30, 31, 35, 38, 40 No connection.
REFOUT 17 14 Analog output Internal reference output. Connect to REFIN when using internal reference.
REFIN 18 15 Analog input Reference input
SCLK 7 8 Digital input Serial clock input of serial peripheral interface (SPI™). Data can be transferred at rates up to 30 MHz. Schmitt-Trigger logic input.
SDO 9 10 Digital output Serial data output. Data are valid on the rising edge of SCLK.
THERMAL PAD Supply input The thermal pad is internally connected to the AVSS supply. It is recommended that the pad be thermally connected to a copper plane for enhanced thermal performance. The pad can be electrically connected to the same potential as the AVSS pin (either negative supply voltage or GND) or left electrically unconnected provided a supply connection is made at the AVSS pin. The AVSS pin must always be connected to either the negative supply voltage or GND, independent of the thermal pad connection.
VOUT 32 21 Analog output Voltage output pin. This is a buffered analog voltage output.
+VSENSE 33 22 Analog input Sense pin for the positive voltage output load connection.
–VSENSE 34 23 Analog input Sense pin for the negative voltage output load connection.