SBAS528C June   2013  – January 2018 DAC7760 , DAC8760

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: AC
    7. 7.7  Timing Requirements: Write Mode
    8. 7.8  Timing Requirements: Readback Mode
    9. 7.9  Timing Requirements: Daisy-Chain Mode
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  DAC Architecture
      2. 8.3.2  Voltage Output Stage
      3. 8.3.3  Current Output Stage
      4. 8.3.4  Internal Reference
      5. 8.3.5  Digital Power Supply
      6. 8.3.6  DAC Clear
      7. 8.3.7  Power-Supply Sequence
      8. 8.3.8  Power-On Reset
      9. 8.3.9  Alarm Detection
      10. 8.3.10 Watchdog Timer
        1. 8.3.10.1 The DACx760 Shares the SPI Bus With Other Devices (Non-DACx760)
      11. 8.3.11 Frame Error Checking
        1. 8.3.11.1 The DACx760 Shares the SPI Bus With Other Devices (Non-DACx760)
      12. 8.3.12 User Calibration
      13. 8.3.13 Programmable Slew Rate
    4. 8.4 Device Functional Modes
      1. 8.4.1 Setting Voltage and Current Output Ranges
      2. 8.4.2 Boost Configuration for IOUT
      3. 8.4.3 Filtering the Current Output (only on the VQFN package)
      4. 8.4.4 HART Interface
        1. 8.4.4.1 For 4-mA to 20-mA Mode
        2. 8.4.4.2 For All Current Output Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI)
        1. 8.5.1.1 SPI Shift Register
        2. 8.5.1.2 Write Operation
        3. 8.5.1.3 Read Operation
        4. 8.5.1.4 Stand-Alone Operation
        5. 8.5.1.5 Daisy-Chain Operation
    6. 8.6 Register Maps
      1. 8.6.1 DACx760 Commands and Register Map
        1. 8.6.1.1 DACx760 Register Descriptions
          1. 8.6.1.1.1 Control Register
          2. 8.6.1.1.2 Configuration Register
          3. 8.6.1.1.3 DAC Registers
          4. 8.6.1.1.4 Reset Register
          5. 8.6.1.1.5 Status Register
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Controlling the VOUT and IOUT Pins
        1. 9.1.1.1 VOUT and IOUT Pins are Independent Outputs, Never Simultaneously Enabled
        2. 9.1.1.2 VOUT and IOUT Pins are Independent Outputs, Simultaneously Enabled
        3. 9.1.1.3 VOUT and IOUT Pins are Tied Together, Never Simultaneously Enabled
      2. 9.1.2 Implementing HART in All Current Output Modes
        1. 9.1.2.1 Using CAP2 Pin on VQFN Package
        2. 9.1.2.2 Using the ISET-R Pin
      3. 9.1.3 Short-Circuit Current Limiting
    2. 9.2 Typical Application
      1. 9.2.1 Voltage and Current Output Driver for Factory Automation and Control, EMC and EMI Protected
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Specifications

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
AVDD to AVSS –0.3 40 V
AVDD to GND –0.3 40 V
AVSS to GND –20 0.3 V
DVDD to GND –0.3 6 V
VOUT to AVSS AVSS AVDD V
VOUT to GND(2) AVSS AVDD V
IOUT to AVSS AVSS AVDD V
IOUT to GND(2) AVSS AVDD V
REFIN to GND –0.3 6 V
REFOUT to GND –0.3 6 V
Current into REFOUT 10 mA
Digital input voltage to GND –0.3 DVDD + 0.3 V
SDO to GND –0.3 DVDD + 0.3 V
ALARM to GND –0.3 6 V
Power dissipation (TJmax – TA)/RθJA W
Junction temperature, TJmax 150 °C
Operating temperature –40 125 °C
Storage temperature, Tstg –65 150 °C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
AVSS tied to GND.

ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
AVDD (AVDD + |AVSS| ≤ 36 V) 10 36 V
AVSS (AVDD + |AVSS| ≤ 36 V) –18 0 V
DVDD, Internal regulator disabled 2.7 5.5 V
Reference input voltage 4.95 5.05 V
External reference current (REFIN = 5 V, outputs off or IOUT enabled) 30 µA
Loop compliance voltage (output = 24 mA)(1) AVDD – 2 V
VIH, Digital input high voltage 2 V
VIL, Digital input low voltage 3.6 V < AVDD < 5.5 V 0.8 V
2.7 V < AVDD < 3.6 V 0.6
Specified performance temperature –40 125 °C
Loop compliance voltage is defined as the voltage at the IOUT pin

Thermal Information

THERMAL METRIC(1) DACx760 UNIT
RHA (VQFN) PWP (HTSSOP)
40 PINS 24 PINS
RθJA Junction-to-ambient thermal resistance 32.9 32.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 17.2 14.1 °C/W
RθJB Junction-to-board thermal resistance 7.5 12.2 °C/W
ψJT Junction-to-top characterization parameter 0.2 0.3 °C/W
ψJB Junction-to-board characterization parameter 7.5 12 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.4 0.63 °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

Electrical Characteristics

At AVDD = 10 V to 36 V, AVSS = –18 V to 0 V, AVDD + |AVSS| ≤ 36 V, GND = 0 V, REFIN = 5-V external, and DVDD = 2.7 V to 5.5 V. For VOUT: RL = 1 kΩ, CL = 200 pF; for IOUT: RL = 300 Ω. All specifications are from TA = –40°C to 125°C, unless otherwise noted. Typical specifications are at 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOLTAGE OUTPUT
Voltage output ranges (normal mode) AVDD ≥ 10 V 0 5 V
AVDD ≥ 10.5 V 0 10
AVSS ≤ –5.5 V, AVDD ≥ 10 V –5 5
AVSS ≤ –10.5 V, AVDD ≥ 10.5 V –10 10
Voltage output range (overrange mode) AVDD ≥ 10 V 0 5.5 V
AVDD ≥ 11.5 V 0 11
AVSS ≤ –6 V, AVDD ≥ 10 V –5.5 5.5
AVSS ≤ –11.5 V, AVDD ≥ 11.5 V –11 11
Resolution DAC8760 16 Bits
DAC7760 12
ACCURACY(2)
Total unadjusted error, TUE TA = –40°C to 125°C –0.07% 0.07% FSR
TA = –40°C to 85°C –0.06% 0.06%
TA = 25°C –0.04% ±0.015% 0.04%
Differential nonlinearity, DNL Monotonic ±1 LSB
Relative accuracy, INL TA = –40°C to 125°C ±0.04% FSR
TA = –40°C to 85°C ±0.022%
Bipolar zero error TA = –40°C to 125°C –7 7 mV
TA = –40°C to 85°C –6 6
TA = 25°C, ±5 V and ±5.5 V –1.5 ±0.5 1.5
TA = 25°C, ±10 V and ±11 V –3 ±1 3
Bipolar zero error temperature coefficient ±1 ppm FSR/°C
Zero-scale error(3) Unipolar range (0 V to 5 V, 0 V to 5.5 V, 0 V to 10 V, 0 V to 11 V) TA = –40°C to 125°C –4 4 mV
TA = –40°C to 85°C –2 2
TA = 25°C –0.6 ±0.1 0.6
Bipolar range (±5 V, ±5.5 V, ±10 V, ±11 V) TA = –40°C to 125°C –10 10 mV
TA = 25°C –3.5 ±1 3.5
Zero-scale error temperature coefficient ±2 ppm FSR/°C
Offset error TA = –40°C to 125°C, unipolar range –4 4 mV
TA = –40°C to 85°C, unipolar range –2 2
TA = 25°C, unipolar range –0.6 ±0.1 0.6
ACCURACY (continued)
Offset error temperature coefficient ±1 ppm FSR/°C
Gain error TA = –40°C to 125°C –0.07% 0.07% FSR
TA = –40°C to 85°C –0.06% 0.06%
TA = 25°C –0.04% ±0.01% 0.04%
Gain error temperature coefficient ±3 ppm FSR/°C
Full-scale error TA = –40°C to 125°C –0.07% 0.07% FSR
TA = –40°C to 85°C –0.06% 0.06%
TA = 25°C –0.04% ±0.01% 0.04%
Full-scale error temperature coefficient ±1 ppm FSR/°C
VOLTAGE OUTPUT (UNIPOLAR AND BIPOLAR MODES)
Headroom AVDD with respect to VOUT full scale 0.5 V
Footroom AVSS with respect to VOUT zero scale –0.5 V
Output voltage drift vs time TA = 125°C, 1000 hrs ±15 ppm FSR
Short-circuit current 30 mA
Load For specified performance 1
Capacitive load stability(4) RL = ∞ 20 nF
RL = 1 kΩ 5 nF
RL = 1 kΩ, external compensation capacitor (4 nF) connected 1 µF
DC output impedance Code = 0x8000 0.3 Ω
DC PSRR(4) No output load 3 10 µV/V
CURRENT OUTPUT
Output current ranges 0 24 mA
0 20
4 20
Resolution DAC8760 16 Bits
DAC7760 12
ACCURACY (0-mA to 20-mA and 0-mA to 24-mA Range)(1)
Total unadjusted error, TUE TA = –40°C to 125°C –0.2% 0.2% FSR
TA = –40°C to 85°C –0.16% 0.16%
TA = 25°C –0.08% ±0.02% 0.08%
Differential nonlinearity, DNL Monotonic ±1 LSB
Relative accuracy, INL(5) TA = –40°C to 125°C ±0.08% FSR
TA = –40°C to 85°C ±0.024%
Offset error TA = –40°C to 125°C –0.17% 0.17% FSR
TA = –40°C to 85°C –0.1% 0.1%
TA = 25°C –0.07% ±0.01% 0.07%
Offset error temperature coefficient ±5 ppm FSR/°C
Full-scale error TA = –40°C to 125°C –0.2% 0.2% FSR
TA = –40°C to 85°C –0.16% 0.16%
TA = 25°C –0.08% ±0.015% 0.08%
Full-scale error temperature coefficient Internal RSET ±5 ppm FSR/°C
External RSET ±10
ACCURACY (0-mA to 20-mA and 0-mA to 24-mA Range) (continued)
Gain error Internal RSET TA = –40°C to 125°C –0.2% 0.2% FSR
TA = –40°C to 85°C –0.15% 0.15%
TA = 25°C –0.08% ±0.01% 0.08%
External RSET TA = –40°C to 125°C –0.17% 0.17%
TA = –40°C to 85°C –0.12% 0.12%
TA = 25°C –0.05% ±0.01% 0.05%
Gain error temperature coefficient Internal RSET ±3 ppm FSR/°C
External RSET ±8
Output current drift vs time TA = 125°C, 1000 hrs Internal RSET ±50 ppm FSR
External RSET ±25
ACCURACY (4-mA TO 20-mA RANGE)(1)
Total unadjusted error, TUE Internal RSET TA = –40°C to 125°C –0.25% 0.25% FSR
TA = 25°C –0.08% ±0.02% 0.08%
External RSET TA = –40°C to 125°C –0.29% 0.29%
TA = –40°C to 85°C –0.25% 0.25%
TA = 25°C –0.1% ±0.02% 0.1%
Differential nonlinearity, DNL Monotonic ±1 LSB
Relative accuracy, INL(5) TA = –40°C to 125°C ±0.08% FSR
TA = –40°C to 85°C ±0.024%
Offset error Internal RSET TA = –40°C to 125°C –0.22% 0.22% FSR
TA = –40°C to 85°C –0.2% 0.2%
External RSET TA = –40°C to 125°C –0.2% 0.2%
TA = –40°C to 85°C –0.18% 0.18%
Internal and External RSET, TA = 25°C –0.07% ±0.01% 0.07%
Offset error temperature coefficient ±3 ppm FSR/°C
Full-scale error Internal RSET TA = –40°C to 125°C –0.25% 0.25% FSR
TA = 25°C –0.08% ±0.015% 0.08%
External RSET TA = –40°C to 125°C –0.29% 0.29%
TA = –40°C to 85°C –0.25% 0.25%
TA = 25°C –0.1% ±0.015% 0.1%
Full-scale error temperature coefficient Internal RSET ±5 ppm FSR/°C
External RSET ±10
Gain error Internal RSET TA = –40°C to 125°C –0.2% 0.2% FSR
TA = –40°C to 85°C –0.15% 0.15%
TA = 25°C –0.08% ±0.01% 0.08%
External RSET TA = –40°C to 125°C –0.16% 0.16%
TA = –40°C to 85°C –0.12% 0.12%
TA = 25°C –0.05% ±0.01% 0.055%
Gain error temperature coefficient Internal RSET ±3 ppm FSR/°C
External RSET ±8
Output current drift vs time TA = 125°C, 1000 hrs Internal RSET ±50 ppm FSR
External RSET ±75
CURRENT OUTPUT(4)
Inductive load 50 mH
DC PSRR 1 µA/V
Output impedance Code = 0x8000 50
EXTERNAL REFERENCE INPUT
Reference input capacitance 10 pF
INTERNAL REFERENCE OUTPUT
Reference output TA = 25°C 4.995 5.005 V
Reference temperature coefficient(4) TA = –40°C to 85°C ±10 ppm/°C
Output noise (0.1 Hz to 10 Hz) TA = 25°C 14 µVPP
Noise spectral density TA = 25°C, 10 kHz 185 nV/√Hz
Capacitive load 600 nF
Load current ±5 mA
Short-circuit current (REFOUT shorted to GND) 25 mA
Load regulation AVDD = 24 V, AVSS = 0 V, TA = 25°C, sourcing 55 µV/mA
AVDD = 24 V, AVSS = 0 V, TA = 25°C, sinking 120
Line regulation ±1.2 µV/V
DVDD INTERNAL REGULATOR
Output voltage AVDD = 24 V 4.6 V
Output load current(4) 10 mA
Load regulation 3.5 mV/mA
Line regulation 1 mV/V
Short-circuit current AVDD = 24 V, to GND 35 mA
Capacitive load stability(4) 2.5 µF
DIGITAL INPUTS
Hysteresis voltage 0.4 V
Input current DVDD-EN, VIN ≤ 5 V –2.7 µA
All pins other than DVDD-EN ±1 µA
Pin capacitance Per pin 10 pF
DIGITAL OUTPUTS
SDO VOL, output low voltage, sinking 200 µA 0.4 V
VOH, output high voltage, sourcing 200 µA DVDD – 0.5 V
High-impedance leakage ±1 µA
ALARM VOL, output low voltage, 10-kΩ pullup resistor to DVDD 0.4 V
VOL, output low voltage, 2.5 mA 0.6 V
High-impedance leakage ±1 µA
High-impedance output capacitance 10 pF
POWER REQUIREMENTS
AIDD Outputs disabled, external DVDD 3 mA
Outputs disabled, internal DVDD 4
Code = 0x8000, VOUT enabled, unloaded 4.6
Code = 0x0000, IOUT enabled 3
Code = 0x0000, both outputs enabled, VOUT unloaded 4.6
AISS Outputs disabled 0.6 mA
Outputs disabled, Internal DVDD 0.6
Code = 0x8000, VOUT enabled, unloaded 2.6
Code = 0x0000, IOUT enabled 0.6
Code = 0x0000, both outputs enabled, VOUT unloaded 2.6
DIDD VIH = DVDD, VIL = GND, interface idle 1 mA
Power dissipation AVDD = 36 V, AVSS = GND, VOUT enabled, unloaded, DVDD = 5 V 140 170 mW
AVDD = 18 V, AVSS = –18 V, VOUT enabled, unloaded, DVDD = 5 V 135
TEMPERATURE
Thermal alarm 142 °C
Thermal alarm hysteresis 18 °C
DAC8760 and DAC7760 current output range is set by writing to RANGE bits in control register at address 0x55.
When powered with AVSS = 0 V, INL and offset error for the 0-V to 5-V and 0-V to 10-V ranges are calculated beginning from code 0x0100 for DAC8760 and from code 0x0010 for DAC7760.
Assumes a footroom of 0.5 V.
Specified by design and characterization; not production tested.
For 0-mA to 20-mA and 0-mA to 24-mA ranges, INL is calculated beginning from code 0x0100 for DAC8760 and from code 0x0010 for DAC7760.

Electrical Characteristics: AC

At AVDD = 10 V to 36 V, AVSS = –18 V to 0 V, AVDD + |AVSS| ≤ 36 V, GND = 0 V, REFIN = 5-V external; and DVDD = 4.5 V to 5.5 V. For VOUT: RL = 2 kΩ, CL = 200 pF; for IOUT: RL = 300 Ω. All specifications –40°C to 125°C, unless otherwise noted. Typical specifications are at 25°C.
PARAMETER(1) TEST CONDITIONS MIN TYP MAX UNIT
DYNAMIC PERFORMANCE
CURRENT OUTPUT
Output current settling time 16-mA step, to 0.1% FSR, no L (inductance) 10 µs
16-mA step, to 0.1% FSR, L < 1 mH 25
AC PSRR 200-mV, 50-Hz or 60-Hz sine wave superimposed on power-supply voltage –75 dB
VOLTAGE OUTPUT
Output voltage settling time 0 V to 10 V, to ±0.03% FSR 22 µs
0 V to 5 V, to ±0.03% FSR 13
Slew rate 0.5 V/µs
Power-on glitch energy 2.5 µV-s
Digital-to-analog glitch energy 0.4 µV-s
Glitch impulse peak amplitude 200 mV
Digital feedthrough 2 nV-s
Output noise (0.1-Hz to 10-Hz bandwidth) 0.1 LSBPP
1 / f corner frequency 100 Hz
Output noise spectral density Measured at 10 kHz 180 nV/√Hz
AC PSRR 200-mV, 50-Hz, or 60-Hz sine wave superimposed on power-supply voltage –75 dB
Specified by characterization, not production tested.

Timing Requirements: Write Mode

At TA = –40°C to 125°C and DVDD = 2.7 V to 5.5 V, unless otherwise noted. See Figure 1 for timing diagram.
PARAMETER(1) MIN MAX UNIT
t1 SCLK cycle time 33 ns
t2 SCLK low time 13 ns
t3 SCLK high time 13 ns
t4 LATCH delay time 13 ns
t5 LATCH high time(2) 40 ns
t6 Data setup time 5 ns
t7 Data hold time 7 ns
t8 LATCH low time 40 ns
t9 CLR pulse width 20 ns
t10 CLR activation time 5 μs
Specified by design, not production tested.
Based on digital interface circuitry only.
When writing to DAC control and config registers, consider the analog output specifications in Electrical Characteristics: AC.

Timing Requirements: Readback Mode

At TA = –40°C to 125°C and DVDD = 2.7 V to 5.5 V, unless otherwise noted. See Figure 2 for timing diagram.
PARAMETER(1) MIN MAX UNIT
t11 SCLK cycle time 60 ns
t12 SCLK low time 25 ns
t13 SCLK high time 25 ns
t14 LATCH delay time 13 ns
t15 LATCH high time 40 ns
t16 Data setup time 5 ns
t17 Data hold time 7 ns
t18 LATCH low time 40 ns
t19 Serial output delay time (CL, SDO = 15 pF) 35 ns
t20 LATCH rising edge to SDO 3-state (CL, SDO = 15 pF) 35 ns
Specified by design, not production tested.

Timing Requirements: Daisy-Chain Mode

At TA = –40°C to 125°C and DVDD = 2.7 V to 5.5 V, unless otherwise noted. See Figure 3 for timing diagram.
PARAMETER(1) MIN MAX UNIT
t21 SCLK cycle time 60 ns
t22 SCLK low time 25 ns
t23 SCLK high time 25 ns
t24 LATCH delay time 13 ns
t25 LATCH high time 40 ns
t26 Data setup time 5 ns
t27 Data hold time 7 ns
t28 LATCH low time 40 ns
t29 Serial output delay time (CL, SDO = 15 pF) 35 ns
Specified by design, not production tested.
DAC7760 DAC8760 tim_write_mode_bas528.gif Figure 1. Write Mode Timing
DAC7760 DAC8760 tim_readback_mode_bas528.gif Figure 2. Readback Mode Timing
DAC7760 DAC8760 tim_daisy_chain_mode_bas528.gif Figure 3. Daisy-Chain Mode Timing

Typical Characteristics

At TA = 25°C, unless otherwise noted.
DAC7760 DAC8760 VREF_drift_plots.png
Figure 4. REFOUT vs Temperature
DAC7760 DAC8760 VREF_Load_Regulation_Plot.png
Figure 6. REFOUT vs Load Current
DAC7760 DAC8760 VREF_noise_PSD_plot.png
Figure 8. REFOUT Noise PSD vs Frequency
DAC7760 DAC8760 REFOUT_transient.png
Figure 10. REFOUT Transient vs Time
DAC7760 DAC8760 AIDD_vs_AVDD_Plot.png
Figure 12. AIDD vs AVDD
DAC7760 DAC8760 DVDD_Load_Regulation_Plot.png
Figure 14. Internal DVDD vs Load Current
DAC7760 DAC8760 VOUT_TUE_vs_Code_unipolar.png
Figure 16. VOUT TUE vs Code (Unipolar Outputs)
DAC7760 DAC8760 VOUT_TUE_overtemp.png
Figure 18. VOUT TUE vs Temperature
DAC7760 DAC8760 VOUT_INL_vs_Code_unipolar_FSR.png
Figure 20. VOUT INL vs Code (Unipolar Outputs)
DAC7760 DAC8760 VOUT_INL_overtemp.png
Figure 22. VOUT INL vs Temperature
DAC7760 DAC8760 VOUT_DNL_vs_Code_unipolar.png
Figure 24. VOUT DNL vs Code (Unipolar Outputs)
DAC7760 DAC8760 VOUT_DNL_overtemp.png
Figure 26. VOUT DNL vs Temperature
DAC7760 DAC8760 VOUT_FSE_overtemp.png
Figure 28. VOUT Full-Scale Error vs Temperature
DAC7760 DAC8760 VOUT_BPZ_overtemp.png
Figure 30. Bipolar Zero Error vs Temperature
DAC7760 DAC8760 VOUT_ZCE_overtemp.png
Figure 32. Zero-Scale Error vs Temperature
DAC7760 DAC8760 C009_SBAS528.png
Figure 34. VOUT (Zero-Scale) vs Load Current
(Source or Sink)
DAC7760 DAC8760 VOUT_settling_falling_plot.png
Figure 36. BP10V Falling
DAC7760 DAC8760 settling_vs_capload_100pF_comp.png
Figure 38. VOUT Settling Time vs LOAD
(100 pF Between VOUT and CMP Pins)
DAC7760 DAC8760 VOUT_power_on_glitch.png
Figure 40. VOUT Power-On Glitch
DAC7760 DAC8760 VOUT_noise_PSD_plot.png
Figure 42. VOUT Noise PSD vs Frequency
DAC7760 DAC8760 VOUT_PIN_Leakage_plot.png
Figure 44. VOUT Hi-Z Leakage Current vs Voltage
DAC7760 DAC8760 VOUT_PSRR_plot.png
Figure 46. AVDD PSRR for VOUT
DAC7760 DAC8760 TUE_0to20mA.png
Figure 48. IOUT TUE vs Code (0 mA to 20 mA)
DAC7760 DAC8760 IOUT_RINT_TUE_overtemp_plot.png
Figure 50. IOUT TUE vs Temperature (Internal RSET)
DAC7760 DAC8760 IOUT_RINT_TUE_vs_supply_plot.png
Figure 52. IOUT TUE vs Supply (Internal RSET)
DAC7760 DAC8760 INL_0to24mA_FSR.png
Figure 54. IOUT INL vs Code (0 mA to 24 mA)
DAC7760 DAC8760 INL_4to20mA_FSR.png
Figure 56. IOUT INL vs Code (4 mA to 20 mA)
DAC7760 DAC8760 IOUT_REXT_INL_overtemp.png
Figure 58. IOUT INL vs Temperature (External RSET)
DAC7760 DAC8760 IOUT_REXT_INL_vs_SUPPLY_plot.png
Figure 60. IOUT INL vs Supply (External RSET)
DAC7760 DAC8760 DNL_0to20mA.png
Figure 62. IOUT DNL vs Code (0 mA to 20 mA)
DAC7760 DAC8760 IOUT_RINT_DNL_overtemp.png
Figure 64. IOUT DNL vs Temperature (Internal RSET)
DAC7760 DAC8760 IOUT_RINT_DNL_vs_supply_plot.png
Figure 66. IOUT DNL vs Supply (Internal RSET)
DAC7760 DAC8760 IOUT_FSE_overtemp.png
Figure 68. IOUT Full-Scale Error vs Temperature
DAC7760 DAC8760 IOUT_GE_overtemp.png
Figure 70. IOUT Gain Error vs Temperature
DAC7760 DAC8760 IOUT_headroom_vs_mA.png
Figure 72. IOUT vs Compliance Headroom Voltage(1)
DAC7760 DAC8760 IOUT_settling_falling_plot.png
Figure 74. 4-mA to 20-mA Falling
DAC7760 DAC8760 IOUT_OUTPUT_ENABLE_GLITCH_plot.png
Figure 76. IOUT Output Enable Glitch
DAC7760 DAC8760 IOUT_noise_PSD.png
Figure 78. IOUT Noise PSD vs Frequency
DAC7760 DAC8760 IOUT_HiZ_Leakage_Plot.png
Figure 80. IOUT Hi-Z Leakage Current vs Voltage
DAC7760 DAC8760 VREF_drift_histo.png
Figure 5. Internal Reference Temperature Drift Histogram
DAC7760 DAC8760 VREF_Line_Regulation_Plot.png
Figure 7. REFOUT vs AVDD
DAC7760 DAC8760 REFOUT_pk_noise_plot.png
Figure 9. Internal Reference, Peak-to-Peak Noise
(0.1 Hz to 10 Hz)
DAC7760 DAC8760 AIDD_AISS_vs_dual_supply_plot.png
Figure 11. AIDD or AISS vs AVDD or AVSS
DAC7760 DAC8760 DVDD_IQ.png
Figure 13. DIDD vs External DVDD
DAC7760 DAC8760 DVDD_PSRR_plot.png
Figure 15. Internal DVDD PSRR vs Frequency
DAC7760 DAC8760 VOUT_TUE_vs_Code.png
Figure 17. VOUT TUE vs Code
DAC7760 DAC8760 VOUT_TUE_vs_SUPPLY_plot.png
Figure 19. VOUT TUE vs Supply
DAC7760 DAC8760 VOUT_INL_vs_Code_FSR.png
Figure 21. VOUT INL vs Code
DAC7760 DAC8760 VOUT_INL_vs_supply_plot.png
Figure 23. VOUT INL vs Supply
DAC7760 DAC8760 VOUT_DNL_vs_Code.png
Figure 25. VOUT DNL vs Code
DAC7760 DAC8760 VOUT_DNL_vs_supply_plot.png
Figure 27. VOUT DNL vs Supply
DAC7760 DAC8760 VOUT_OE_overtemp.png
Figure 29. Offset Error vs Temperature
DAC7760 DAC8760 VOUT_GE_overtemp.png
Figure 31. Gain Error vs Temperature
DAC7760 DAC8760 C010_SBAS528.png
Figure 33. VOUT (Full-Scale) vs Load Current
(Source or Sink)
DAC7760 DAC8760 VOUT_settling_rising_plot.png
Figure 35. BP10V Rising
DAC7760 DAC8760 settling_vs_capload_0comp.png
Figure 37. VOUT Settling Time vs Load
(No Compensation Capacitor)
DAC7760 DAC8760 settling_vs_capload_470pF_comp.png
Figure 39. VOUT Settling Time vs LOAD
(470 pF Between VOUT and CMP Pins)
DAC7760 DAC8760 VOUT_digital_to_analog_glitch.png
Figure 41. VOUT Digital-to-Analog Glitch
DAC7760 DAC8760 VOUT_pk_noise_plot.png
Figure 43. VOUT, Peak-to-Peak Noise (0.1 Hz to 10 Hz)
DAC7760 DAC8760 VOUT_SSC_overtemp_plot.png
Figure 45. VOUT Short-Circuit Current vs Temperature
DAC7760 DAC8760 TUE_0to24mA.png
Figure 47. IOUT TUE vs Code (0 mA to 24 mA)
DAC7760 DAC8760 TUE_4to20mA.png
Figure 49. IOUT TUE vs Code (4 mA to 20 mA)
DAC7760 DAC8760 IOUT_REXT_TUE_overtemp_plot.png
Figure 51. IOUT TUE vs Temperature (External RSET)
DAC7760 DAC8760 IOUT_REXT_TUE_vs_supply_plot.png
Figure 53. IOUT TUE vs Supply (External RSET)
DAC7760 DAC8760 INL_0to20mA_FSR.png
Figure 55. IOUT INL vs Code (0 mA to 20 mA)
DAC7760 DAC8760 IOUT_RINT_INL_overtemp.png
Figure 57. IOUT INL vs Temperature (Internal RSET)
DAC7760 DAC8760 IOUT_RINT_INL_vs_SUPPLY_plot.png
Figure 59. IOUT INL vs Supply (Internal RSET)
DAC7760 DAC8760 DNL_0to24mA.png
Figure 61. IOUT DNL vs CODE (0 mA to 24 mA)
DAC7760 DAC8760 DNL_4to20mA.png
Figure 63. IOUT DNL vs Code (4 mA to 20 mA)
DAC7760 DAC8760 IOUT_REXT_DNL_overtemp_plot.png
Figure 65. IOUT DNL vs Temperature (External RSET)
DAC7760 DAC8760 IOUT_REXT_DNL_vs_supply_plot.png
Figure 67. IOUT DNL vs Supply (External RSET)
DAC7760 DAC8760 IOUT_OFFSET_overtemp.png
Figure 69. IOUT Offset Error vs Temperature
DAC7760 DAC8760 IOUT_compliance_overtemp.png
Figure 71. Compliance Headroom Voltage(1) vs Temperature
DAC7760 DAC8760 IOUT_settling_rising_plot.png
Figure 73. 4-mA to 20-mA Rising
DAC7760 DAC8760 IOUT_POR_glitch_plot.png
Figure 75. IOUT Power-On Glitch
Compliance voltage headroom is defined as the drop from AVDD pin to the IOUT pin.
DAC7760 DAC8760 IOUT_code_to_code_glitch.png
Figure 77. IOUT Digital-to-Analog Glitch
DAC7760 DAC8760 IOUT_pk_pk_noise_nA.png
Figure 79. IOUT Peak-to-Peak Noise vs Time
(0.1 Hz to 10 Hz)
DAC7760 DAC8760 IOUT_PSRR_plot.png
Figure 81. IOUT PSRR vs Frequency