DLPS140B March   2019  – May 2022 DLP2000

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  System Mounting Interface Loads
    9. 6.9  Physical Characteristics of the Micromirror Array
    10. 6.10 Micromirror Array Optical Characteristics
    11. 6.11 Window Characteristics
    12. 6.12 Chipset Component Usage Specification
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Control Serial Interface
      3. 7.3.3 High Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Window Characteristics and Optics
      1. 7.5.1 Optical Interface and System Image Quality
        1. 7.5.1.1 Numerical Aperture and Stray Light Control
        2. 7.5.1.2 Pupil Match
        3. 7.5.1.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
      2. 11.2.2 Device Markings
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High level output voltage VCC = 1.65 V
IOH = –2 mA
1.20 V
VOL Low level output voltage VCC = 1.95 V
IOL = –2 mA
0.45 V
IIL Low level input current(1)(2) VCC = 1.95 V
VI = 0 V
52 nA
IIH High level input current(1)(2) VCC = 1.95 V
VI = 1.95 V
41 nA
CURRENT
ICC Current at VCC = 1.95 V DCLK Frequency = 77 MHz 30 mA
IOFFSET Current at VOFFSET = 8.75 V(3) 1.5 mA
IBIAS Current at VBIAS = 16.5 V(3)(4) Three global resets within time period = 200 µs 1.3 mA
IRESET Current at VRESET = –10.5 V Three global resets within time period = 200 µs 1.2 mA
POWER
PCC Power at VCC = 1.95 V(5) DCLK Frequency = 77 MHz 26 59 mW
POFFSET Power at VOFFSET = 8.75 V(5) 5 13 mW
PBIAS Power at VBIAS = 16.5 V(5) Three global resets within time period = 200 µs 9 22 mW
PRESET Power at VRESET = –10.5 V(5) Three global resets within time period = 200 µs 4 13 mW
PTOTAL Supply power dissipation total 44 107 mW
CAPACITANCE
CIN Input capacitance f = 1 MHz 10 pF
COUT Output capacitance f = 1 MHz 10 pF
Includes LVCMOS pins only
LVCMOS input pins do not have pullup or pulldown configurations.
To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than 8.75 V.
When DRC_OEZ = high, the internal reset drivers are tri-stated and IBIAS standby current is 3.8 mA.
Nominal values are measured with VCC = 1.8 V, VOFFSET = 8.5 V, VBIAS = 16 V, and VRESET = –10 V.