DLPS119B December   2018  – May 2022 DLP2010NIR

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
      1. 6.13.1 Software Requirements
    14. 6.14 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Low-Speed Interface
      3. 7.3.3 High-Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Optical Interface and System Image Quality
        1. 7.5.1.1 Numerical Aperture and Stray Light Control
        2. 7.5.1.2 Pupil Match
        3. 7.5.1.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Device Markings
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • FQJ|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3 Power Supply Sequencing Requirements

GUID-8EE92B5A-A3E0-4D0F-B57F-BD714B944F58-low.gif
A. Refer to Table 9-1 and Figure 9-2 for critical power-up sequence delay requirements.
B. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in Recommended Operating Conditions. OEMs may find that the most reliable way to ensure this is to power VOFFSET prior to VBIAS during power-up and to remove VBIAS prior to VOFFSET during power-down. Refer to Table 9-1 and Figure 9-2 for power-up delay requirements.
C. To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit shown in Recommended Operating Conditions.
D. When system power is interrupted, the ASIC driver initiates hardware power-down that disables VBIAS, VRESET and VOFFSET after the Micromirror Park Sequence. Software power-down disables VBIAS, VRESET, and VOFFSET after the Micromirror Park Sequence through software control.
E. Drawing is not to scale and details are omitted for clarity.
Figure 9-1 Power Supply Sequencing Requirements (Power Up and Power Down)
Table 9-1 Power-Up Sequence Delay Requirement
PARAMETER MIN MAX UNIT
tDELAY Delay requirement from VOFFSET power up to VBIAS power up 2 ms
VOFFSET Supply voltage level during power–up sequence delay (see Figure 9-2) 6 V
VBIAS Supply voltage level during power–up sequence delay (see Figure 9-2) 6 V
GUID-091BB8A4-8766-45B0-B32D-439EE6031EDD-low.gif
Note: Refer to Table 9-1 for VOFFSET and VBIAS supply voltage levels during power-up sequence delay.
Figure 9-2 Power-Up Sequence Delay Requirement