DLPS144F july   2018  – july 2023 DLP230NP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Display Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Low-Speed Interface
      3. 7.3.3 High-Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Power Density Calculation
    8. 7.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Power-Up Procedure
      2. 8.3.2 Power Supply Power-Down Procedure
      3. 8.3.3 Power Supply Sequencing Requirements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Device Nomenclature
      3. 9.1.3 Device Markings
    2. 9.2 Chipset Resources
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-3359D530-7E13-49F3-8F08-E76CB9E9F6E1-low.gif Figure 5-1 FQP Package, 54-Pin CLGA (Bottom View)
Table 5-1 Pin Functions – Connector Pins
PIN(1) TYPE SIGNAL DATA RATE DESCRIPTION PACKAGE NET LENGTH(2) (mm)
NAME NO.
DATA INPUTS
D_N(0) A2 I SubLVDS Double Data, negative 1.96
D_N(1) A1 I SubLVDS Double Data, negative 1.42
D_N(2) C1 I SubLVDS Double Data, negative 1.35
D_N(3) B4 I SubLVDS Double Data, negative 3.36
D_N(4) F5 I SubLVDS Double Data, negative 4.29
D_N(5) D4 I SubLVDS Double Data, negative 3.20
D_N(6) E1 I SubLVDS Double Data, negative 1.76
D_N(7) F3 I SubLVDS Double Data, negative 2.66
D_P(0) A3 I SubLVDS Double Data, positive 1.97
D_P(1) B1 I SubLVDS Double Data, positive 1.49
D_P(2) C2 I SubLVDS Double Data, positive 1.44
D_P(3) A4 I SubLVDS Double Data, positive 3.45
D_P(4) E5 I SubLVDS Double Data, positive 4.32
D_P(5) D5 I SubLVDS Double Data, positive 3.27
D_P(6) E2 I SubLVDS Double Data, positive 1.85
D_P(7) F2 I SubLVDS Double Data, positive 2.75
DCLK_N C3 I SubLVDS Double Clock, negative 1.94
DCLK_P D3 I SubLVDS Double Clock, positive 2.02
CONTROL INPUTS
LS_WDATA A12 I LPSDR(1) Single Write data for low speed interface 2.16
LS_CLK B12 I LPSDR Single Clock for low-speed interface 3.38
DMD_DEN_ARSTZ B14 I LPSDR Single Asynchronous reset DMD signal. A low signal places the DMD in reset. A high signal releases the DMD from reset and places it in active mode. 0.67
DMD_DEN_ARSTZ F1 I LPSDR Single 14.90
LS_RDATA C13 O LPSDR Single Read data for low-speed interface 2.44
POWER
VBIAS(3) A15 Power Supply voltage for positive bias level at micromirrors
VBIAS(3) A5 Power
VOFFSET(3) F13 Power Supply voltage for HVCMOS core logic. Supply voltage for stepped high level at micromirror address electrodes.
Supply voltage for offset level at micromirrors
VOFFSET(3) F4 Power
VRESET B15 Power Supply voltage for negative reset level at micromirrors
VRESET B5 Power
VDD(3) C15 Power Supply voltage for LVCMOS core logic. Supply voltage for LPSDR inputs.
Supply voltage for normal high level at micromirror address electrodes
VDD C5 Power
VDD D14 Power
VDD D15 Power
VDD E14 Power
VDD E15 Power
VDD F14 Power
VDD F15 Power
VDDI C14 Power Supply voltage for SubLVDS receivers
VDDI C4 Power
VDDI D13 Power
VDDI E13 Power
VSS A13 Ground Common return.
Ground for all power
VSS A14 Ground
VSS B13 Ground
VSS B2 Ground
VSS B3 Ground
VSS C12 Ground
VSS D1 Ground
VSS D12 Ground
VSS D2 Ground
VSS E12 Ground
VSS E3 Ground
VSS E4 Ground
VSS F12 Ground
(1) Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR). See JESD209B.
(2) Net trace lengths inside the package:
Relative dielectric constant for the FQP ceramic package is 9.8.
Propagation speed = 11.8 / sqrt (9.8) = 3.769 in/ns.
Propagation delay = 0.265 ns/inch = 265 ps/in = 10.43 ps/mm
(3) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are also required.
Table 5-2 Pin Functions – Test Pads
NUMBER SYSTEM BOARD
A6 Do not connect.
A7 Do not connect.
A8 Do not connect.
A9 Do not connect.
A10 Do not connect.
A11 Do not connect.
F6 Do not connect.
F7 Do not connect.
F8 Do not connect.
F9 Do not connect.
F10 Do not connect.
F11 Do not connect.