DLPS254 January   2026 DLP390TP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5.     11
    6. 5.5  Thermal Information
    7. 5.6  Electrical Characteristics
    8. 5.7  Switching Characteristics
    9. 5.8  Timing Requirements
    10.     16
    11. 5.9  System Mounting Interface Loads
    12. 5.10 Micromirror Array Physical Characteristics
    13. 5.11 Micromirror Array Optical Characteristics
    14. 5.12 Window Characteristics
    15. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 LPSDR Low-Speed Interface
      3. 6.3.3 High-Speed Interface
      4. 6.3.4 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Window Aperture Illumination Overfill Calculation
    9. 6.9 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.9.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.9.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.9.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.9.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Temperature Sensor Diode
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. 9 Layout
    1. 9.1 Layout Guidelines
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.4 Recommended Operating Conditions

Over operating free-air temperature range and supply voltages (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the Recommended Operating Conditions limits
PARAMETER DESCRIPTION MIN TYP MAX UNIT
SUPPLY VOLTAGE RANGE
VDD Supply voltage for LVCMOS core logic(1)(2)
Supply voltage for LPSDR low-speed interface		 1.71 1.8 1.95 V
VDDI Supply voltage for SubLVDS receivers(1)(2) 1.71 1.8 1.95 V
VOFFSET Supply voltage for HVCMOS and micromirror electrode(1)(2)(3) 9.5 10 10.5 V
VBIAS Supply voltage for mirror electrode(1)(2) 17.5 18 18.5 V
VRESET Supply voltage for micromirror electrode(1)(2) –14.5 –14 –13.5 V
|VDDI - VDD| Supply voltage delta (absolute value)(1)(2)(4) 0.3 V
|VBIAS - VOFFSET| Supply voltage delta (absolute value)(1)(2)(5) 10.5 V
|VBIAS - VRESET| Supply voltage delta (absolute value)(1)(2)(6) 33 V
LPSDR INTERFACE
VIH High-level input voltage 0.7 × VDD V
VIL Low-level input voltage 0.3 x VDD V
VIH (AC) AC input high voltage 0.8 × VDD VDD + 0.3 V
VIL (AC) AC input low voltage –0.3 0.2 × VDD V
VHyst Input Hysteresis 0.1 × VDD 0.4 × VDD V
fmax_LS Clock frequency for low speed interface LS_CLK (7) 108 130 MHz
DCDIN LSIF duty cycle distortion (LS_CLK) (7) 44 56 %
SUBLVDS INTERFACE
|VID| LVDS differential input voltage magnitude(8) 150 250 350 mV
VCM Common mode voltage(8) 700 900 1100 mV
VSUBLVDS SubLVDS voltage(8) 525 1275 mV
ZLINE Line differential impedance (PWB/trace) 90 100 110 Ω
ZIN Internal differential termination resistance(10) 80 100 120 Ω
TEMPERATURE DIODE
ITEMP_DIODE Max current source into Temperature Diode 120 µA
ENVIRONMENTAL
TARRAY Array temperature, long-term operation(9)(10)(11)(12) 0 40 to 70 °C
TDP-AVG Average dew point temperature, (non-condensing)(13) 28 °C
TDP-ELR Elevated dew point temperature range, (non-condensing)(14) 28 36 °C
CTELR Cumulative time in elevated dew point temperature range 24 Months
QAP-LL Window Aperture illumination overfill(15)(16)(17) 17 W/cm2
ILLUMINATION LPCW, RGB Laser and LED
ILLUV Illumination, wavelength < 410nm(9)(19) 10 mW/cm2
ILLVIS Illumination power at wavelengths ≥ 410nm and ≤ 800nm(18)(19) 40 W/cm2
ILLIR Illumination, wavelength between > 800nm(19) 10 mW/cm2
ILLBLU Illumination power at wavelengths ≥ 410nm and ≤ 475nm(18)(19) 12.8 W/cm2
ILLBLU1 Illumination power at wavelengths ≥ 410nm and ≤ 440nm(18)(19) 2.0 W/cm2
(1) The following power supplies are required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are required to operate the DMD.
(2) All voltage values are with respect to the VSS ground pins.
(3) VOFFSET supply transients must fall within the specified max voltages.
(4) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than the specified limit.
(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit.
(6) To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than the specified limit.
(7) LS_CLK must run as specified to meet internal DMD timing for reset waveform commands.
(8) Refer to the SubLVDS timing requirements in Timing Requirements.
(9) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination reduces device lifetime.
(10) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point (TP1) shown in Figure 6-2 and the package thermal resistance using the Micromirror Array Temperature Calculation
(11) Long-term is defined as the usable life of the device.
(12) Per Figure 5-1, the maximum operational array temperature is derated based on the micromirror landed duty cycle that the DMD experiences in the end application. See Micromirror Landed-on/Landed-off Duty cycle for a definition of micromirror landed duty cycle.
(13) The average over time (including storage and operating) is that the device is not in the elevated dew point temperature range.
(14) Exposure to dew point temperatures in the elevated range during storage and operation is limited to less than a total cumulative time of CTELR..
(15) Applies to the region defined in Figure 5-2
(16) The active area of the DMD is surrounded by an aperture on the inside of the DMD window surface that masks structures of the DMD device assembly for normal view. The aperture is sized to anticipate several optical conditions. Overfill light illuminating the area outside the active array can scatter and create adverse effects on the performance of an end application using the DMD. Minimizing the light flux incident outside the active array is a design requirement of the illumination optical system. Depending on the particular optical architecture and assembly tolerances of the optical system, the amount of overfill light on the outside of the active array may cause system performance degradation.
(18) The maximum allowable optical power incident on the DMD is limited by the maximum optical power density for each wavelength range specified and the micromirror array temperature (TARRAY).