DLPS229A December   2022  – February 2024 DLP4621-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
      1. 5.4.1 Illumination Overfill Diagram
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Timing Requirements
      1.      Electrical and Timing Diagrams
    8. 5.8  Switching Characteristics
      1. 5.8.1 LPSDR and Test Load Circuit Diagrams
    9. 5.9  System Mounting Interface Loads
      1.      System Interface Loads Diagram
    10. 5.10 Micromirror Array Physical Characteristics
      1. 5.10.1 Micromirror Array Physical Characteristics Diagram
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 SubLVDS Data Interface
      2. 6.3.2 Low Speed Interface for Control
      3. 6.3.3 DMD Voltage Supplies
      4. 6.3.4 Asynchronous Reset
      5. 6.3.5 Temperature Sensing Diode
        1. 6.3.5.1 Temperature Sense Diode Theory
    4. 6.4 System Optical Considerations
      1. 6.4.1 Numerical Aperture and Stray Light Control
      2. 6.4.2 Pupil Match
      3. 6.4.3 Illumination Overfill
    5. 6.5 DMD Image Performance Specification
    6. 6.6 Micromirror Array Temperature Calculation
      1. 6.6.1 Monitoring Array Temperature Using the Temperature Sense Diode
    7. 6.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application Overview
      2. 7.2.2 Input Image Resolution
      3. 7.2.3 Reference Design
      4. 7.2.4 Application Mission Profile Consideration
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power Supply Power-Up Procedure
      2. 7.3.2 Power Supply Power-Down Procedure
      3. 7.3.3 Power Supply Sequencing Requirements
    4. 7.4 Layout Guidelines
    5. 7.5 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
      2. 8.1.2 Device Markings
    2. 8.2 Third-Party Products Disclaimer
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 DMD Handling
    8. 8.8 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • FQX|120
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted) (1)(2)
MIN NOM MAX UNIT
SUPPLY VOLTAGE 
VDD Supply voltage for LVCMOS core logic
Supply voltage for LPSDR low-speed interface		 1.65 1.8 1.95 V
VDDI Supply voltage for SubLVDS receivers 1.65 1.8 1.95 V
VOFFSET Supply voltage for HVCMOS and micromirror electrode(3) 8.25 8.5 8.75 V
VBIAS Supply voltage for mirror electrode 15.5 16 16.5 V
VRESET Supply voltage for micromirror electrode –9.5 –10 –10.5 V
|VDDI – VDD| Supply voltage delta (absolute value)(4) 0.3 V
|VBIAS – VOFFSET| Supply voltage delta (absolute value)(5) 8.75 V
|VBIAS – VRESET| Supply voltage delta (absolute value)(6) 28 V
LOW-SPEED LPDSR INTERFACE
fclock_LS Clock frequency for low speed interface LS_CLK 108 120 MHz
DCDIN LSIF duty cycle distortion (LS_CLK) 44% 56% —
SUBLVDS INTERFACE
fclock_HS Clock frequency for high-speed interface DCLK 300 540 MHz
DCDIN LVDS duty cycle distortion (DCLK) 44% 56% —
|VID| LVDS differential input voltage magnitude(7) 150 250 350 mV
VCM Common mode voltage(7) 700 900 1100 mV
VSUBLVDS SubLVDS voltage(7) 525 1275 mV
ZLINE Line differential impedance (PWB/trace) 90 100 110 Ω
ZIN Internal differential termination resistance (8) 80 100 120 Ω
100Ω differential PCD trace 6.35 152.4 mm
ENVIRONMENTAL
TARRAY Array Temperature(9)(11) –40 105 °C
Illumination
ILLUV Illumination, wavelength < 395nm(10) 2 mW/cm2
ILLOVERFILL Illumination overfill maximum heat load in the area shown in the Illumination Overfill Diagram. 90 mW/mm2
(1) Recommended Operating Conditions are applicable after the DMD is installed in the final product.
(2) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.
(3) VOFFSET supply transients must fall within specified min and max voltages.
(4) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than the specified limit.
(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit.
(6) To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than the specified limit.
(7) See Figure 5-6 and Figure 5-7.
(8) See Figure 5-8.
(9) DMD Active Array temperature can be calculated as shown in the Micromirror Array Temperature Calculation section.
(10) The maximum operation conditions for operating temperature and UV illumination shall not be implemented simultaneously.
(11) Operating profile information for device micromirror landed duty-cycle and temperature may be provided if requested.