DLPS229A December   2022  – February 2024 DLP4621-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
      1. 5.4.1 Illumination Overfill Diagram
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Timing Requirements
      1.      Electrical and Timing Diagrams
    8. 5.8  Switching Characteristics
      1. 5.8.1 LPSDR and Test Load Circuit Diagrams
    9. 5.9  System Mounting Interface Loads
      1.      System Interface Loads Diagram
    10. 5.10 Micromirror Array Physical Characteristics
      1. 5.10.1 Micromirror Array Physical Characteristics Diagram
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 SubLVDS Data Interface
      2. 6.3.2 Low Speed Interface for Control
      3. 6.3.3 DMD Voltage Supplies
      4. 6.3.4 Asynchronous Reset
      5. 6.3.5 Temperature Sensing Diode
        1. 6.3.5.1 Temperature Sense Diode Theory
    4. 6.4 System Optical Considerations
      1. 6.4.1 Numerical Aperture and Stray Light Control
      2. 6.4.2 Pupil Match
      3. 6.4.3 Illumination Overfill
    5. 6.5 DMD Image Performance Specification
    6. 6.6 Micromirror Array Temperature Calculation
      1. 6.6.1 Monitoring Array Temperature Using the Temperature Sense Diode
    7. 6.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application Overview
      2. 7.2.2 Input Image Resolution
      3. 7.2.3 Reference Design
      4. 7.2.4 Application Mission Profile Consideration
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power Supply Power-Up Procedure
      2. 7.3.2 Power Supply Power-Down Procedure
      3. 7.3.3 Power Supply Sequencing Requirements
    4. 7.4 Layout Guidelines
    5. 7.5 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
      2. 8.1.2 Device Markings
    2. 8.2 Third-Party Products Disclaimer
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 DMD Handling
    8. 8.8 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • FQX|120
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Timing Requirements

Device electrical characteristics are over Recommended Operating ConditionsRecommended Operating ConditionsRecommended Operating ConditionsRecommended Operating Conditions unless otherwise noted
MIN NOM MAX UNIT
Low-Speed Interface
tr Rise slew rate(1)(2) (20% to 80%) × VDD 0.25 V/ns
tf Fall slew rate(1)(2) (80% to 20%) × VDD 0.25 V/ns
tc Cycle time LS_CLK 7.7 8.3 ns
tW(H) Pulse duration LS_CLK high(3) 50% to 50% reference points 3.1 ns
tW(L) Pulse duration LS_CLK low(3) 50% to 50% reference points 3.1 ns
tsu Setup time(3) LS_WDATA valid before LS_CLK↑ or LS_CLK↓ 1.5 ns
th Hold time(3) LS_WDATA valid after LS_CLK↑ or LS_CLK↓ 1.5 ns
tWINDOW Window time Setup time + hold time 3 ns
tDERATING Window time derating For each 0.25V/ns reduction in slew rate below 1V/ns 0.35 ns
High-Speed Interface
tr Rise slew rate(2) 20% to 80% reference points 0.7 1 V/ns
tf Fall slew rate(2) 80% to 20% reference points 0.7 1 V/ns
tc Cycle time DCLK (3) 1.79 1.85 ns
tW(H) Pulse duration DCLK high(3) 50% to 50% reference points 0.79 ns
tW(L) Pulse duration DCLK low(3) 50% to 50% reference points 0.79 ns
tWINDOW Window time(3)(4) Setup time + Hold time 0.3 ns
tLVDS-EN+REFGEN Power-up receiver(5) 2000 ns
(1) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 5-2.
(2) See Figure 5-3.
(3) See Figure 5-4.
(4) See Figure 5-5.
(5) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.