DLPS159C April 2019 – February 2023 DLP470NE
PRODUCTION DATA
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VOLTAGE SUPPLY | |||||
VCC | LVCMOS logic supply voltage#DLPS1599720 | 1.65 | 1.8 | 1.95 | V |
VOFFSET | Mirror electrode and HVCMOS voltage#DLPS1599720#DLPS1593066 | 9.5 | 10 | 10.5 | V |
VBIAS | Mirror electrode voltage#DLPS1599720 | 17.5 | 18 | 18.5 | V |
VRESET | Mirror electrode voltage#DLPS1599720 | –14.5 | –14 | –13.5 | V |
|VBIAS – VOFFSET| | Supply voltage difference (absolute value)#DLPS1597978 | 10.5 | V | ||
|VBIAS – VRESET| | Supply voltage difference (absolute value)#DLPS1597936 | 33 | V | ||
LVCMOS INTERFACE | |||||
VIH(DC) | DC input high voltage#DLPS1595892 | 0.7 × VCC | VCC + 0.3 | V | |
VIL(DC) | DC input low voltage#DLPS1595892 | –0.3 | 0.3 × VCC | V | |
VIH(AC) | AC input high voltage#DLPS1595892 | 0.8 × VCC | VCC + 0.3 | V | |
VIL(AC) | AC input low voltage#DLPS1595892 | –0.3 | 0.2 × VCC | V | |
tPWRDNZ | PWRDNZ pulse duration#DLPS1595746 | 10 | ns | ||
SCP INTERFACE | |||||
ƒSCPCLK | SCP clock frequency#DLPS159808 | 500 | kHz | ||
tSCP_PD | Propagation delay, Clock to Q, from rising–edge of SCPCLK to valid SCPDO#DLPS1599761 | 0 | 900 | ns | |
tSCP_NEG_ENZ | Time between falling-edge of SCPENZ and the first rising- edge of SCPCLK | 1 | µs | ||
tSCP_POS_ENZ | Time between falling-edge of SCPCLK and the rising-edge of SCPENZ | 1 | µs | ||
tSCP_DS | SCPDI Clock setup time (before SCPCLK falling edge)#DLPS1599761 | 800 | ns | ||
tSCP_DH | SCPDI Hold time (after SCPCLK falling edge)#DLPS1599761 | 900 | ns | ||
tSCP_PW_ENZ | SCPENZ inactive pulse duration (high level) | 2 | µs | ||
LVDS INTERFACE | |||||
ƒCLOCK | Clock frequency for LVDS interface (all channels), DCLK#DLPS1595806 | 400 | MHz | ||
|VID| | Input differential voltage (absolute value)#DLPS159398 | 150 | 300 | 440 | mV |
VCM | Common mode voltage#DLPS159398 | 1100 | 1200 | 1300 | mV |
VLVDS | LVDS voltage#DLPS159398 | 880 | 1520 | mV | |
tLVDS_RSTZ | Time required for LVDS receivers to recover from PWRDNZ | 2000 | ns | ||
ZIN | Internal differential termination resistance | 80 | 100 | 120 | Ω |
ZLINE | Line differential impedance (PWB/trace) | 90 | 100 | 110 | Ω |
ENVIRONMENTAL | |||||
TARRAY | Array temperature, long–term operational#DLPS1594684#DLPS1593629#DLPS1599678 | 10 | 40 to 70#DLPS1593159 | °C | |
Array temperature, short–term operational#DLPS1593629#DLPS1595797 | 0 | 10 | °C | ||
TWINDOW | Window temperature – operational#T5021507-2#T4852280-14 | 85 | °C | ||
|TDELTA| | Absolute temperature delta between any point on the window edge and the ceramic test point TP1#DLPS1594914#DLPS1595061 | 14 | °C | ||
TDP -AVG | Average dew point temperature (non–condensing)#DLPS1595716 | 28 | °C | ||
TDP-ELR | Elevated dew point temperature range (non-condensing)#DLPS1593111 | 28 | 36 | °C | |
CTELR | Cumulative time in elevated dew point temperature range | 24 | Months | ||
ILLUMINATION (Lamp) |
|||||
L | Operating system luminance #DLPS1595061 | 4000 | lm | ||
ILLUV | Illumination wavelengths < 395 nm#DLPS1594684 | 0.68 | 2.00 | mW/cm2 | |
ILLVIS | Illumination wavelengths between 395 nm and 800 nm | Thermally limited | mW/cm2 | ||
ILLIR | Illumination wavelengths > 800 nm | 10 | mW/cm2 | ||
ILLθ | Illumination marginal ray angle#T4852280-14 | 55 | deg | ||
ILLUMINATION (Solid State) | |||||
L | Operating system luminance #DLPS1595061 |
5500 |
lm | ||
ILLUV | Illumination wavelengths < 436 nm#DLPS1594684 |
0.45 |
mW/cm2 | ||
ILLVIS | Illumination wavelengths between 436 nm and 800 nm |
Thermally Limited |
mW/cm2 | ||
ILLIR | Illumination wavelengths > 800 nm |
10 |
mW/cm2 | ||
ILLθ | Illumination marginal ray angle#T4852280-14 |
55 |
deg |