DLPS159C April   2019  – February 2023 DLP470NE

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Capacitance at Recommended Operating Conditions
    8. 6.8  Timing Requirements
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 DMD Die Temperature Sensing
  9. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Layers
      2. 10.2.2 Impedance Requirements
      3. 10.2.3 Trace Width, Spacing
        1. 10.2.3.1 Voltage Signals
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
      2. 11.2.2 Device Markings
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
      1.      Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1 Absolute Maximum Ratings

Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
MINMAXUNIT
SUPPLY VOLTAGES
VCCSupply voltage for LVCMOS core logic#DLPS15994–0.52.3V
VOFFSETSupply voltage for HVCMOS and micromirror electrode#DLPS15994#DLPS1597921–0.511V
VBIASSupply voltage for micromirror electrode#DLPS15994–0.519V
VRESETSupply voltage for micromirror electrode#DLPS15994–15–0.3V
|VBIAS – VOFFSET|Supply voltage difference (absolute value)#DLPS159785611V
|VBIAS – VRESET|Supply voltage difference (absolute value)#DLPS159509934V
INPUT VOLTAGES
Input voltage for all other LVCMOS input pins#DLPS15994–0.5VCC + 0.5V
|VID|Input differential voltage (absolute value)#DLPS159455500mV
IIDInput differential current#DLPS15990576.3mA
Clocks
ƒCLOCKClock frequency for LVDS interface, DCLK_C400MHz
ƒCLOCKClock frequency for LVDS interface, DCLK_D400MHz
ENVIRONMENTAL
TARRAY and TWINDOWTemperature, operating#DLPS1595778090°C
Temperature, non–operating#DLPS1595778–4090°C
|TDELTA|Absolute temperature delta between any point on the window edge and the ceramic test point TP1 #DLPS159233330°C
TDPDew point temperature, operating and non–operating (noncondensing)81°C
(1) All voltages are referenced to common ground VSS. VBIAS, VCC, VOFFSET, and VRESET power supplies are all required for proper DMD operation. VSS must also be connected.
(2) VOFFSET supply transients must fall within specified voltages.
(3) Exceeding the recommended allowable voltage difference between VBIAS and VOFFSET may result in excessive current draw.
(4) Exceeding the recommended allowable voltage difference between VBIAS and VRESET may result in excessive current draw.
(5) This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.
(6) LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.
(7) The highest temperature of the active array (as calculated using Micromirror Array Temperature Calculation) or of any point along the window edge as defined in GUID-07E49ADF-BA45-491F-86FB-ADBE885C5B80.html#DLPS1599630. The locations of thermal test points TP2, TP3, TP4 and TP5 in GUID-07E49ADF-BA45-491F-86FB-ADBE885C5B80.html#DLPS1599630 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, use that point.
(8) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in GUID-07E49ADF-BA45-491F-86FB-ADBE885C5B80.html#DLPS1599630. The window test points TP2, TP3, TP4 and TP5 shown in GUID-07E49ADF-BA45-491F-86FB-ADBE885C5B80.html#DLPS1599630 are intended to result in the worst case delta. If a particular application causes another point on the window edge to result in a larger delta temperature, use that point.