DLPS021 September 2019 DLP470TP
PRODUCTION DATA.
Optimum layout practices requires the board to have a matched impedance of 50 Ω ±10% for all signals. Table 10 lists the exceptions to these imprdance requirements.
Signal Type | Signal Name | Impedance (Ω) |
---|---|---|
A, B, C, and D channel LVDS differential pairs | DDxP(0:15), DDxN(0:15) | 100 ±10% differential across each pair |
DCLKx_P, DCLKx_N | ||
SCTRL_CP, SCTRL_CN |