DLPS021 September   2019 DLP470TP

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Application (LED Configuration)
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Capacitance at Recommended Operating Conditions
    8. 6.8  Timing Requirements
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Temperature Sensor Diode
  9. Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Layers
      2. 10.2.2 Impedance Requirements
      3. 10.2.3 Trace Width, Spacing
        1. 10.2.3.1 Voltage Signals
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and Functions

FQN Package
250-Pin CLGA
Bottom View
DLP470TP DS-47-4K-s316-Pins.gif

CAUTION

To ensure reliable, long-term operation of the .47” 4K UHD S316 DMD, it is critical to properly manage the layout and operation of the signals identified in the table below.

For specific details and guidelines, refer to the PCB Design Requirements for TI DLP Pico TRP Digital Micromirror Devices application report before designing the board.

Pin Functions(1)

PIN I/O(2) SIGNAL DATA
RATE
INTERNAL
TERMINATION
DESCRIPTION TRACE
LENGTH
(mm)
NAME NO.
D_AN(0) B5 I LVDS DDR Differential Data negative 8.98747
D_AN(1) B1 8.97919
D_AN(2) B3 9.21384
D_AN(3) F2 9.39087
D_AN(4) D2 9.54145
D_AN(5) D3 9.27074
D_AN(6) C7 9.02002
D_AN(7) B9 9.36086
D_AN(8) C9 9.0579
D_AN(9) D7 9.38275
D_AN(10) B10 9.06869
D_AN(11) B13 9.04589
D_AN(12) C11 9.46624
D_AN(13) D10 9.09742
D_AN(14) C12 9.09742
D_AN(15) D12 9.42403
D_AP(0) B4 I LVDS DDR Differential Data positive 9.08754
D_AP(1) C1 9.07961
D_AP(2) B2 9.31429
D_AP(3) F3 9.50425
D_AP(4) E2 9.65859
D_AP(5) D4 9.3646
D_AP(6) C6 9.12022
D_AP(7) B8 9.46125
D_AP(8) C8 9.15806
D_AP(9) D6 9.48372
D_AP(10) B11 9.1687
D_AP(11) B12 9.14277
D_AP(12) C10 9.5666
D_AP(13) D9 9.19838
D_AP(14) C13 9.40291
D_AP(15) D13 9.52321
D_BN(0) R5 I LVDS DDR Differential Data negative 9.10693
D_BN(1) R1 8.96073
D_BN(2) P3 9.10705
D_BN(3) T2 9.06795
D_BN(4) N3 9.48088
D_BN(5) N1 9.85003
D_BN(6) P7 9.06246
D_BN(7) R7 9.64953
D_BN(8) P9 9.37131
D_BN(9) N7 9.40519
D_BN(10) R10 9.06869
D_BN(11) R13 9.0549
D_BN(12) P11 9.45471
D_BN(13) N10 9.09742
D_BN(14) P12 9.37251
D_BN(15) N12 9.43745
D_BP(0) R4 I LVDS DDR Differential Data positive 9.21371
D_BP(1) P1 9.06786
D_BP(2) R3 9.20554
D_BP(3) R2 9.17689
D_BP(4) M3 9.59954
D_BP(5) N2 9.94411
D_BP(6) P6 9.16937
D_BP(7) R6 9.75042
D_BP(8) P8 9.47818
D_BP(9) N6 9.51286
D_BP(10) R11 9.16197
D_BP(11) R12 9.15849
D_BP(12) P10 9.55989
D_BP(13) N9 9.20509
D_BP(14) P13 9.46661
D_BP(15) N13 9.52992
D_CN(0) C15 I LVDS DDR Differential Data negative 9.41325
D_CN(1) C16 9.03449
D_CN(2) D15 9.52465
D_CN(3) C18 9.02915
D_CN(4) B17 9.04775
D_CN(5) D18 9.02956
D_CN(6) B18 9.36461
D_CN(7) D21 9.02729
D_CN(8) C20 9.11449
D_CN(9) B20 9.00902
D_CN(10) C22 9.05166
D_CN(11) C24 8.99211
D_CN(12) B22 9.0163
D_CN(13) A25 9.15166
D_CN(14) D25 9.17016
D_CN(15) A23 9.03448
D_CP(0) C14 I LVDS DDR Differential Data positive 9.50523
D_CP(1) C17 9.1478
D_CP(2) D16 9.64383
D_CP(3) C19 9.12978
D_CP(4) B16 9.13427
D_CP(5) D19 9.13402
D_CP(6) B19 9.46507
D_CP(7) D22 9.12774
D_CP(8) C21 9.2337
D_CP(9) B21 9.12611
D_CP(10) C23 9.15286
D_CP(11) D24 9.09244
D_CP(12) B23 9.14094
D_CP(13) B25 9.25197
D_CP(14) E25 9.2705
D_CP(15) A24 9.14097
D_DN(0) P15 I LVDS DDR Differential Data negative 9.39144
D_DN(1) P16 9.03449
D_DN(2) N15 9.4803
D_DN(3) P18 8.96795
D_DN(4) R17 9.04775
D_DN(5) N18 9.02956
D_DN(6) R18 9.36461
D_DN(7) N21 9.02729
D_DN(8) P20 9.11449
D_DN(9) R20 9.00902
D_DN(10) P22 9.03774
D_DN(11) P24 8.99211
D_DN(12) R22 8.9767
D_DN(13) T25 9.13373
D_DN(14) N25 9.15485
D_DN(15) T23 9.03448
D_DP(0) P14 I LVDS DDR Differential Data positive 9.49852
D_DP(1) P17 9.1316
D_DP(2) N16 9.60619
D_DP(3) P19 9.06186
D_DP(4) R16 9.14735
D_DP(5) N19 9.12731
D_DP(6) R19 9.45836
D_DP(7) N22 9.12103
D_DP(8) P21 9.22699
D_DP(9) R21 9.1194
D_DP(10) P23 9.13666
D_DP(11) N24 9.08573
D_DP(12) R23 9.07467
D_DP(13) R25 9.22784
D_DP(14) M25 9.26064
D_DP(15) T24 9.14037
SCTRL_AN E4 I LVDS DDR Differential Serial control negative 9.44429
SCTRL_AP F4 I LVDS DDR Differential Serial control positive 9.5515
SCTRL_BN N4 I LVDS DDR Differential Serial control negative 9.80493
SCTRL_BP M4 I LVDS DDR Differential Serial control positive 9.89456
SCTRL_CN E23 I LVDS DDR Differential Serial control negative 9.19249
SCTRL_CP F23 I LVDS DDR Differential Serial control positive 9.29266
SCTRL_DN M23 I LVDS DDR Differential Serial control negative 9.19321
SCTRL_DP L23 I LVDS DDR Differential Serial control positive 9.28668
DCLK_AN C5 I LVDS Differential Clock negative 9.4868
DCLK_AP C4 I LVDS Differential Clock positive 9.58794
DCLK_BN P5 I LVDS Differential Clock negative 9.67816
DCLK_BP P4 I LVDS Differential Clock positive 9.78601
DCLK_CN E21 I LVDS Differential Clock negative 9.54268
DCLK_CP E22 I LVDS Differential Clock positive 9.6428
DCLK_DN M21 I LVDS Differential Clock negative 9.54268
DCLK_DP M22 I LVDS Differential Clock positive 9.63609
SCPCLK B6 I LVCMOS Pull down Serial communications port clock. Active only when SCPENZ is logic low.
SCPDI A7 I LVCMOS SDR Pull down Serial communications port data input. Synchronous to SCPCLK rising edge.
SCPENZ A8 I LVCMOS Pull down Serial communications port enable active low.
SCPDO B7 O LVCMOS SDR Serial communications port output.
RESET_ADDR(0) T8 I LVCMOS Pull down Reset driver address select
RESET_ADDR(1) R9
RESET_ADDR(2) T7
RESET_ADDR(3) R8
RESET_MODE(0) T5 I LVCMOS Pull down Reset driver mode select
RESET_SEL(0) T4 I LVCMOS Pull down Reset driver level select
RESET_SEL(1) L2 I LVCMOS Pull down Reset driver level select
RESET_STROBE L4 I LVCMOS Pull down Rising edge latches in RESET_ADDR, RESET_MODE, & RESET_SEL
PWRDNZ A4 I LVCMOS Pull down Active low device reset
RESET_OEZ T14 I LVCMOS Pull up Active low output enable for internal reset driver circuits
RESET_IRQZ R14 O LVCMOS Active low output interrupt to DLP display controller
EN_OFFSET C3 O LVCMOS Active high enable for external VOFFSET regulator
PG_OFFSET A2 I LVCMOS Pull up Active low fault from external VOFFSET regulator
TEMP_N A16 I Analog Temperature sensor diode cathode
TEMP_P B14 I Analog Temperature sensor diode anode
NO CONNECT E10, E11, E12, E13, E14, E15, E16, E17, M12, M13, M14, M15, K2, G2, L24, F24, M16, M17, M18, E18 NC Do not connect on DLP system board.
SCP_TEST_MUX A5 I LVCMOS Pull down Connect to ground on DLP system board
VBIAS(3) A19, A20, T19, T20 P Analog Supply voltage for positive bias level of micromirror reset signal.
VRESET(3) A10, A11, T10, T11 P Analog Supply voltage for negative reset level of micromirror reset signal
VOFFSET(3) A1, C25, P25, T1, T13 P Analog Supply voltage for HVCMOS logic. Supply voltage for positive offset level of micromirror reset signal. Supply voltage for stepped high voltage at micromirror address electrodes.
VCC(3) A13, A14, D1, E1, F21, F22, G3, G4, G21, G22, G23, H3, H4, H21, H22, H23, J3, J4, J21, J22, J23, K3, K4, K21, K22, K23, L21, L22, M1, M2 P Analog Supply voltage for LVCMOS core. Supply voltage for positive offset level of micromirror reset signal during Power down. Supply voltage for normal high level at micromirror address electrodes.
VSS(4) A3, A6, A9, A12, A15, A17, A18,A21, A22, B15, B24, C2, D5, D8, D11, D14, D17, D20, D23, E3, E24, L3, M24, N5, N8, N11, N14, N17, N20, N23, P2, R15, R24, T3, T6, T9, T12, T15, T16, T17, T18, T21, T22 G Device ground. Common return for all power.
The .47” 4K UHD 2xLVDS series 316 DMD is a component of one or more DLP chipsets. Use the .47” 4K UHD 2xLVDS series 316 DMD in conjunction with other components of the applicable DLP chipset to make sure there is reliable operation. These include components that contain or implement TI DMD control technology. TI DMD control technology consists of the TI technology and devices used for operating or controlling a DLP DMD.
I = Input, O = Output, P = Power, G = Ground, NC = No connect.
VBIAS, VCC, VOFFSET, and VRESET power supplies must be connected for proper DMD operation.
VSS must be connected for proper DMD operation.