6.4 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is implied when operating the device above or below these limits.
|
MIN |
NOM |
MAX |
UNIT |
VOLTAGE SUPPLY |
VCC |
LVCMOS logic supply voltage(1) |
1.65 |
1.8 |
1.95 |
V |
VOFFSET |
Mirror electrode and HVCMOS voltage(1)(2) |
9.5 |
10 |
10.5 |
V |
VBIAS |
Mirror electrode voltage(1) |
17.5 |
18 |
18.5 |
V |
VRESET |
Mirror electrode voltage(1) |
–14.5 |
–14 |
–13.5 |
V |
|VBIAS – VOFFSET| |
Supply voltage difference (absolute value)(3) |
|
|
10.5 |
V |
|VBIAS – VRESET| |
Supply voltage difference (absolute value)(4) |
|
|
33 |
V |
LVCMOS INTERFACE |
VIH(DC) |
DC input high voltage(5) |
0.7 × VCC |
|
VCC + 0.3 |
V |
VIL(DC) |
DC input low voltage(5) |
–0.3 |
|
0.3 × VCC |
V |
VIH(AC) |
AC input high voltage(5) |
0.8 × VCC |
|
VCC + 0.3 |
V |
VIL(AC) |
AC input low voltage(5) |
–0.3 |
|
0.2 × VCC |
V |
tPWRDNZ |
PWRDNZ pulse duration(6) |
10 |
|
|
ns |
SCP INTERFACE |
ƒSCPCLK |
SCP clock frequency(7) |
|
|
500 |
kHz |
tSCP_PD |
Propagation delay, clock to Q, from rising–edge of SCPCLK to valid SCPDO(8) |
0 |
|
900 |
ns |
tSCP_NEG_ENZ |
Time between falling-edge of SCPENZ and the first rising-edge of SCPCLK |
1 |
|
|
µs |
tSCP_POS_ENZ |
Time between falling-edge of SCPCLK and the rising-edge of SCPENZ |
1 |
|
|
µs |
tSCP_DS |
SCPDI clock setup time (before SCPCLK falling edge)(8) |
800 |
|
|
ns |
tSCP_DH |
SCPDI hold time (after SCPCLK falling edge)(8) |
900 |
|
|
ns |
tSCP_PW_ENZ |
SCPENZ inactive pulse duration (high level) |
2 |
|
|
µs |
LVDS INTERFACE |
ƒCLOCK |
Clock frequency for LVDS interface (all channels), DCLK(9) |
|
|
400 |
MHz |
|VID| |
Input differential voltage (absolute value)(10) |
150 |
300 |
440 |
mV |
VCM |
Common mode voltage(10) |
1100 |
1200 |
1300 |
mV |
VLVDS |
LVDS voltage(10) |
880 |
|
1520 |
mV |
tLVDS_RSTZ |
Time required for LVDS receivers to recover from PWRDNZ |
|
|
2000 |
ns |
ZIN |
Internal differential termination resistance |
80 |
100 |
120 |
Ω |
ZLINE |
Line differential impedance (PWB/trace) |
90 |
100 |
110 |
Ω |
ENVIRONMENTAL |
TARRAY |
Array temperature, long–term operational(11)(12)(13)(14) |
0 |
|
40 to 70(13) |
°C |
Array temperature, short–term operational, 25 hr max(12)(15) |
–20 |
|
–10 |
°C |
Array temperature, short–term operational, 500 hr max(12)(15) |
–10 |
|
0 |
°C |
Array temperature, short–term operational, 500 hr max(12)(15) |
70 |
|
75 |
°C |
TWINDOW |
Window temperature – operational(16)(17) |
|
|
85 |
°C |
|TDELTA| |
Absolute temperature delta between any point on the window edge and the ceramic test point TP1(18) |
|
|
14 |
°C |
TDP -AVG |
Average dew point temperature (non–condensing)(19) |
|
|
24 |
°C |
TDP-ELR |
Elevated dew point temperature range (non-condensing)(20) |
28 |
|
36 |
°C |
CTELR |
Cumulative time in elevated dew point temperature range |
|
|
6 |
months |
ILLUV |
Illumination wavelengths < 400 nm(11) |
|
|
2.00 |
mW/cm2 |
ILLVIS |
Illumination wavelengths between 400 nm and 700 nm |
Thermally limited |
mW/cm2 |
ILLIR |
Illumination wavelengths > 700 nm |
|
|
10 |
mW/cm2 |
ILLθ |
Illumination marginal ray angle(17) |
|
|
55 |
degrees |
(1) All voltages are referenced to common ground VSS. VBIAS, VCC, VOFFSET, and VRESET power supplies are all required for proper DMD operation. VSS must also be connected.
(2) VOFFSET supply transients must fall within specified max voltages.
(5) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, “Low-Power Double Data Rate (LPDDR)” JESD209B. Tester conditions for V
IH and V
IL.
- Frequency = 60 MHz, maximum rise time = 2.5 ns @ (20% - 80%)
- Frequency = 60 MHz, maximum fall time = 2.5 ns @ (80% - 20%)
(6) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tristates the SCPDO output pin.
(7) The SCP clock is a gated clock. Duty cycle must be 50% ± 10%. SCP parameter is related to the frequency of DCLK.
(10) See
Figure 5 LVDS waveform requirements.
(13) Per
Figure 1, the maximum operational array temperature derates based on the micromirror landed duty cycle that the DMD experiences in the end application. See
Micromirror Landed-On/Landed-Off Duty Cycle for a definition of micromirror landed duty cycle.
(14) Long-term is defined as the useful life of the device.
(15) Short-term is the total cumulative time over the useful life of the device.
(16) The locations of thermal test points TP2, TP3, TP4, and TP5 shown in
Figure 10 are intended to measure the highest window edge temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular application causes additional points on the window edge to be at a higher temperature, add test points to those locations.
(17) Ensure that the maximum marginal ray angle of the incoming illumination light at any point in the micromirror array (including pond of micromirrors (POM)), does not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM) contributes to thermal limitations described in this document, and may negatively affect lifetime.
(18) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in
Figure 10. The window test points TP2, TP3, TP4, and TP5 shown in
Figure 10 are intended to result in the worst case delta temperature. If a particular application causes another point on the window edge to result in a larger delta in temperature, use that point.
(19) The average over time (including storage and operating) that the device is not in the ‘elevated dew point temperature range'.
(20) Limit exposure to dew point temperatures in the elevated range during storage and operation to less than a total cumulative time of CTELR.