DLPS021 September   2019 DLP470TP

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Application (LED Configuration)
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Capacitance at Recommended Operating Conditions
    8. 6.8  Timing Requirements
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Temperature Sensor Diode
  9. Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Layers
      2. 10.2.2 Impedance Requirements
      3. 10.2.3 Trace Width, Spacing
        1. 10.2.3.1 Voltage Signals
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Timing Requirements

MIN NOM MAX UNIT
SCP(1)
tr Rise slew rate 20% to 80% reference points 1 3 V/ns
tf Fall slew rate 80% to 20% reference points 1 3 V/ns
LVDS(2)
tr Rise slew rate 20% to 80% reference points 0.7 1 V/ns
tf Fall slew rate 80% to 20% reference points 0.7 1 V/ns
tC Clock cycle DCLK_A, LVDS pair 2.5 ns
DCLK_B, LVDS pair 2.5 ns
DCLK_C, LVDS pair 2.5 ns
DCLK_D, LVDS pair 2.5 ns
tW Pulse duration DCLK_A LVDS pair 1.19 1.25 ns
DCLK_B LVDS pair 1.19 1.25 ns
DCLK_C LVDS pair 1.19 1.25 ns
DCLK_D LVDS pair 1.19 1.25 ns
tSu Setup time D_A(15:0) before DCLK_A, LVDS pair 0.275 ns
D_B(15:0) before DCLK_B, LVDS pair 0.275 ns
D_C(15:0) before DCLK_C, LVDS pair 0.275 ns
D_D(15:0) before DCLK_D, LVDS pair 0.275 ns
SCTRL_A before DCLK_A, LVDS pair 0.275 ns
SCTRL_B before DCLK_B, LVDS pair 0.275 ns
SCTRL_C before DCLK_C, LVDS pair 0.275 ns
SCTRL_D before DCLK_D, LVDS pair 0.275 ns
th Hold time D_A(15:0) after DCLK_A, LVDS pair 0.195 ns
D_B(15:0) after DCLK_B, LVDS pair 0.195 ns
D_C(15:0) after DCLK_C, LVDS pair 0.195 ns
D_D(15:0) after DCLK_D, LVDS pair 0.195 ns
SCTRL_A after DCLK_A, LVDS pair 0.195 ns
SCTRL_B after DCLK_B, LVDS pair 0.195 ns
SCTRL_C after DCLK_C, LVDS pair 0.195 ns
SCTRL_D after DCLK_D, LVDS pair 0.195 ns
LVDS(2)
tSKEW Skew time Channel B relative to channel A(3)(4), LVDS pair –1.25 1.25 ns
tSKEW Skew time Channel D relative to channel C(5)(6), LVDS pair –1.25 1.25 ns
See Figure 3 for rise time and fall time for SCP.
See Figure 5 for timing requirements for LVDS.
Channel A (Bus A) includes the following LVDS pairs: DCLK_AN and DCLK_AP, SCTRL_AN and SCTRL_AP, D_AN(15:0), and D_AP(15:0).
Channel B (Bus B) includes the following LVDS pairs: DCLK_BN and DCLK_BP, SCTRL_BN and SCTRL_BP, D_BN(15:0), and D_BP(15:0).
Channel C (Bus C) includes the following LVDS pairs: DCLK_CN and DCLK_CP, SCTRL_CN and SCTRL_CP, D_CN(15:0), and D_CP(15:0).
Channel D (Bus D) includes the following LVDS pairs: DCLK_DN and DCLK_DP, SCTRL_DN and SCTRL_DP, D_DN(15:0), and D_DP(15:0).
DLP470TP scp-timing-requirements_dlps109.gif
SCPCLK falling–edge captures SCPDI
SCPCLK rising–edge launches SCPDO
See Recommended Operating Conditions for fSCPCLK, tSCP_DS, tSCP_DH, and tSCP_PD specifications.
Figure 2. SCP Timing Requirements

See Timing Requirements for tr and tf specifications and conditions shown in Figure 3.) For output timing analysis, make sure to consider the effect that tester pin electronics and its transmission line can cause. Use IBIS or other simulation tools to correlate the timing reference load to a system environment. (See Figure 4.)

DLP470TP scp_req_for_rise_fall.gifFigure 3. SCP Requirements for Rise and Fall
DLP470TP test_load_circuit.gifFigure 4. Test Load Circuit for Output Propagation Measurement
DLP470TP lvds_waveform_req.gif
See Recommended Operating Conditions for VCM, VID, and VLVDS specifications and conditions.
Figure 5. LVDS Waveform Requirements
DLP470TP dlp480e_LVDS_Timing_dlps092.gifFigure 6. Timing Requirements

See Timing Requirements for timing requirements and LVDS pairs per channel (bus) defining D_P(?:0) and D_N(?:0).