DLPS125C Data sheet

DLPS125C November 2018 – July 2023 DLP4710

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

FQL|100
- MCLG032C

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS⁽²⁾	MIN	TYP	MAX	UNIT
CURRENT
I_DD	Supply current: VDD⁽³⁾ ⁽⁴⁾	V_DD = 1.95 V			260	mA
I_DD	Supply current: VDD⁽³⁾ ⁽⁴⁾	V_DD = 1.8 V		180		mA
I_DDI	Supply current: VDDI⁽³⁾ ⁽⁴⁾	V_DDI = 1.95 V			62	mA
I_DDI	Supply current: VDDI⁽³⁾ ⁽⁴⁾	V_DDI = = 1.8 V		40		mA
I_OFFSET	Supply current: VOFFSET⁽⁵⁾ ⁽⁶⁾	V_OFFSET = 10.5 V			7.4	mA
I_OFFSET	Supply current: VOFFSET⁽⁵⁾ ⁽⁶⁾	V_OFFSET = 10 V		6.3		mA
I_BIAS	Supply current: VBIAS⁽⁵⁾ ⁽⁶⁾	VBIAS = 18.5 V			1.1	mA
I_BIAS	Supply current: VBIAS⁽⁵⁾ ⁽⁶⁾	VBIAS = 18 V		0.9		mA
I_RESET	Supply current: VRESET⁽⁶⁾	VRESET = –14.5 V			5.4	mA
I_RESET	Supply current: VRESET⁽⁶⁾	VRESET = –14 V		4.4		mA
POWER⁽⁷⁾
P_DD	Supply power dissipation: VDD⁽³⁾ ⁽⁴⁾	VDD = 1.95 V			507	mW
P_DD	Supply power dissipation: VDD⁽³⁾ ⁽⁴⁾	VDD = 1.8 V		324		mW
P_DDI	Supply power dissipation: VDDI⁽³⁾ ⁽⁴⁾	VDDI = 1.95 V			120.9	mW
P_DDI	Supply power dissipation: VDDI⁽³⁾ ⁽⁴⁾	VDD = 1.8 V		72		mW
P_OFFSET	Supply power dissipation: VOFFSET⁽⁵⁾ ⁽⁶⁾	VOFFSET = 10.5 V			77.7	mW
P_OFFSET	Supply power dissipation: VOFFSET⁽⁵⁾ ⁽⁶⁾	VOFFSET = 10 V		63		mW
P_BIAS	Supply power dissipation: VBIAS⁽⁵⁾ ⁽⁶⁾	VBIAS = 18.5 V			20.35	mW
P_BIAS	Supply power dissipation: VBIAS⁽⁵⁾ ⁽⁶⁾	VBIAS = 18 V		16.2		mW
P_RESET	Supply power dissipation: VRESET⁽⁶⁾	VRESET = –14.5 V			78.3	mW
P_RESET	Supply power dissipation: VRESET⁽⁶⁾	VRESET = –14 V		61.6		mW
P_TOTAL	Supply power dissipation: Total			536.8	804.25	mW
LPSDR INPUT⁽⁸⁾
V_IH(DC)	DC input high voltage⁽⁹⁾		0.7 × VDD		VDD + 0.3	V
V_IL(DC)	DC input low voltage⁽⁹⁾		–0.3		0.3 × VDD	V
V_IH(AC)	AC input high voltage⁽⁹⁾		0.8 × VDD		VDD + 0.3	V
V_IL(AC)	AC input low voltage⁽⁹⁾		–0.3		0.2 × VDD	V
∆V_T	Hysteresis ( V_T+ – V_T– )	Figure 6-10	0.1 × VDD		0.4 × VDD	V
I_IL	Low–level input current	VDD = 1.95 V; V_I = 0 V	–100			nA
I_IH	High–level input current	VDD = 1.95 V; V_I = 1.95 V			100	nA
LPSDR OUTPUT⁽¹⁰⁾
V_OH	DC output high voltage	I_OH = –2 mA	0.8 × VDD			V
V_OL	DC output low voltage	I_OL = 2 mA			0.2 × VDD	V
CAPACITANCE
C_IN	Input capacitance LPSDR	ƒ = 1 MHz			10	pF
C_IN	Input capacitance SubLVDS	ƒ = 1 MHz			20	pF
C_OUT	Output capacitance	ƒ = 1 MHz			10	pF
C_RESET	Reset group capacitance	ƒ = 1 MHz; (1080 × 240) micromirrors	400		450	pF

(1) Device electrical characteristics are over ^{Recommended Operating Conditions} unless otherwise noted.

(2) All voltage values are with respect to the ground pins (VSS).

(3) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.

(4) Supply power dissipation based on non–compressed commands and data.

(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.

(6) Supply power dissipation based on 3 global resets in 200 µs.

(7) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are also required.

(8) LPSDR specifications are for pins LS_CLK and LS_WDATA.

(9) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.

(10) LPSDR specification is for pin LS_RDATA.