DLPS170B September   2020  – April 2022 DLP471TE

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Temperature Sensor Diode
  9. Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Impedance Requirements
    3. 10.3 Layers
    4. 10.4 Trace Width, Spacing
    5. 10.5 Power
    6. 10.6 Trace Length Matching Recommendations
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
      2. 11.2.2 Device Markings
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Recommended Operating Conditions

Over operating free-air temperature range and supply voltages (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the Recommended Operating Conditions limits.
MIN TYP MAX UNIT
SUPPLY VOLTAGES (1) (2)
VDD Supply voltage for LVCMOS core logic and low speed interface (LSIF) 1.71 1.8 1.95 V
VDDA Supply voltage for high speed serial interface (HSSI) receivers 1.71 1.8 1.95 V
VOFFSET Supply voltage for HVCMOS and micromirror electrode(3) 9.5 10 10.5 V
VBIAS Supply voltage for micromirror electrode 17.5 18 18.5 V
VRESET Supply voltage for micromirror electrode –14.5 –14 –13.5 V
| VDDA – VDD | Supply voltage delta, absolute value(4) 0.3 V
| VBIAS – VOFFSET | Supply voltage delta, absolute value(5) 10.5 V
| VBIAS – VRESET | Supply voltage delta, absolute value 33 V
LVCMOS INPUT
VIH High level input voltage(6)  0.7 × VDD V
VIL Low level input voltage(6) 0.3 × VDD V
LOW SPEED SERIAL INTERFACE (LSIF)
fCLOCK LSIF clock frequency (LS_CLK)(7) 108 120 130 MHz
DCDIN LSIF duty cycle distortion (LS_CLK) 44% 56%
| VID | LSIF differential input voltage magnitude(7) 150 350 440 mV
VLVDS LSIF voltage(7) 575 1520 mV
VCM Common mode voltage(7) 700 900 1300 mV
ZLINE Line differential impedance (PWB/trace) 90 100 110 Ω
ZIN Internal differential termination resistance 80 100 120 Ω
HIGH SPEED SERIAL INTERFACE (HSSI)
fCLOCK HSSI clock frequency (DCLK)(8) 1.2 1.6 GHz
DCDIN HSSI duty cycle distortion (DCLK) 44% 50% 56%
| VID | Data HSSI differential input voltage magnitude data lane(8) 100 600 mV
| VID | CLK HSSI differential input voltage magnitude clock Lane(8) 295 600 mV
VCMDC Data Input common mode voltage (DC) data lane(8) 200 600 800 mV
VCMDC CLK Input common mode voltage (DC) clk lane(8) 200 600 800 mV
VCMACp-p AC peak to peak (ripple) on common mode voltage of data lane and clock lane(8)   100 mV
ZLINE Line differential impedance (PWB/trace) 100 Ω
ZIN Internal differential termination resistance. ( RXterm ) 80 100 120 Ω
ENVIRONMENTAL
TARRAY Array temperature, long-term operational(9)(10)(11)(12)(13) 10 40 to 70  °C
Array temperature, short-term operational, 500-hr max(10)(14) 0 10 °C
TWINDOW Window temperature, operational(15) 85 °C
|TDELTA| Absolute temperature delta between any point on the window edge and the ceramic test point TP1(16) 14 °C
TDP-AVG Average dew point temperature (non–condensing)(17) 28 °C
TDP-ELR Elevated dew point temperature range (non-condensing)(18) 28 36 °C
CTELR Cumulative time in elevated dew point temperature range 24 months
ILLθ Illumination marginal ray angle(19) 55 °
LAMP ILLUMINATION
ILLUV Illumination wavelength < 395 nm(9) 0.68 2 mW/cm2
ILLVIS Illumination wavelengths between 395 nm and 800 nm(13) 36.8 W/cm2
ILLIR Illumination wavelength > 800 nm 10 mW/cm2
SOLID STATE ILLUMINATION
ILLUV Illumination wavelength < 410 nm(9) 3 mW/cm2
ILLVIS Illumination wavelengths between 410 nm and 800 nm(13) 44.9 W/cm2
ILLIR Illumination wavelength > 800 nm 10 mW/cm2
The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point (TP1) shown in Figure 7-1 and the package thermal resistance using the Micromirror Array Temperature Calculation.
Per Figure 6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Micromirror Landed-On/Landed-Off Duty Cycle for a definition of micromirror landed duty cycle.
The maximum optical power that can be incident on the DMD is limited by the maximum optical power density and the micromirror array temperature
The locations of thermal test points TP2, TP3, TP4, and TP5 shown in Figure 7-1 are intended to measure the highest window edge
temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular
application causes additional points on the window edge to be at a higher temperature, test points should be added to those locations.
Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in Figure 7-1. The window test points TP2, TP3, TP4, and TP5 shown in  Figure 7-1 are intended to result in the worst case delta
temperature. If a particular application causes another point on the window edge to result in a larger delta in temperature, that point
should be used.
The average over time (including storage and operating) that the device is not in the ‘elevated dew point temperature range'.
Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR.
The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including pond of micromirrors (POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM) will contribute to thermal limitations described in this document, and may negatively affect lifetime.
GUID-353CB0E3-CC5D-4990-A013-64BE173A2983-low.gif Figure 6-1 Maximum Recommended Array Temperature—Derating Curve