DLPS258 Data sheet

DLPS258 August 2025 DLP472NP

PRODUCTION DATA

5.8 Timing Requirements

Over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

			MIN	NOM	MAX	UNIT
LPSDR
t_f	Fall slew rate ⁽²⁾	(80% to 20%) × V_DD⁽⁵⁾	0.25			V/ns
t_c	Cycle time LS_CLK⁽⁵⁾	50% to 50% reference points⁽⁵⁾	7.7	8.3		ns
t_r	Rise slew rate ⁽¹⁾	(30% to 80%) × V_DD⁽⁶⁾	1		3	V/ns
t_f	Fall slew rate ⁽¹⁾	(70% to 20%) x V_DD⁽⁶⁾	1		3	V/ns
t_r	Rise slew rate ⁽²⁾	(20% to 80%) × V_DD⁽⁶⁾	0.25			V/ns
t_W(H)	Pulse duration LS_CLK high	50% to 50% reference points⁽⁵⁾	3.1			ns
t_W(L)	Pulse duration LS_CLK low	50% to 50% reference points⁽⁵⁾	3.1			ns
t_WINDOW	Window time⁽¹⁾⁽³⁾	Setup time + Hold time⁽⁵⁾	3			ns
t_DERATING	Window time derating⁽¹⁾⁽³⁾	For each 0.25V/ns reduction in slew rate below 1 V/ns⁽⁸⁾		0.35		ns
t_su	Setup time	LS_WDATA valid before LS_CLK⁽⁵⁾			1.5	ns
t_h	Hold time	LS_WDATA valid after LS_CLK⁽⁵⁾			1.5	ns
SubLVDS
t_r	Rise slew rate	20% to 80% reference points⁽⁷⁾	0.7	1		V/ns
t_f	Fall slew rate	80% to 20% reference points⁽⁷⁾	0.7	1		V/ns
t_c	Cycle time D_CLK⁽⁹⁾	50% to 50% reference points⁽⁹⁾	1.35	1.39		ns
t_W(H)	Pulse duration DCLK high	50% to 50% reference points⁽⁹⁾	0.7			ns
t_W(L)	Pulse duration DCLK low	50% to 50% reference points⁽⁹⁾	0.7			ns
t_su	Setup time	DATA valid before D_CLK⁽⁹⁾			0.17	ns
t_h	Hold time	DATA valid after D_CLK⁽⁹⁾			0.17	ns
t_WINDOW	Window time	Setup time + Hold time⁽⁹⁾⁽¹⁰⁾			0.25	ns
t_POWER	Power-up receiver⁽⁴⁾				200	ns

(1) Specification is for LS_CLK and LS_WDATA pins. Refer to the LPSDR input rise and fall slew rate in Figure 5-3.

(2) Specification is for the DMD_DEN_ARSTZ pin. Refer to the LPSDR input rise and fall slew rate in Figure 5-3.

(3) Window time derating example: 0.5V/ns slew rate increases the window time by 0.7ns, from 3ns to 3.7ns.

(4) The specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.

(10) See Figure 5-7.