DLPS258 Data sheet

DLPS258 August 2025 DLP472NP

PRODUCTION DATA

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Mechanical Data (Package|Pins)

FQY|174
- MCLG050

Thermal pad, mechanical data (Package|Pins)

Orderable Information

5.4 Recommended Operating Conditions

Over operating free-air temperature range and supply voltages (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the Recommended Operating Conditions limits.

		MIN	TYP	MAX	UNIT
SUPPLY VOLTAGE RANGE
VDD	Supply voltage for LVCMOS core logic⁽¹⁾⁽²⁾ Supply voltage for LPSDR low-speed interface⁽¹⁾⁽²⁾	1.71	1.8	1.95	V
VDDI	Supply voltage for SubLVDS receivers⁽¹⁾⁽²⁾	1.71	1.8	1.95	V
VOFFSET	Supply voltage for HVCMOS and micromirror electrode⁽¹⁾⁽²⁾⁽³⁾	9.5	10	10.5	V
VBIAS	Supply voltage for mirror electrode⁽¹⁾⁽²⁾	17.5	18	18.5	V
VRESET	Supply voltage for micromirror electrode⁽¹⁾⁽²⁾	–14.5	–14	–13.5	V
\|VDDI- VDD\|	Supply voltage delta (absolute value)⁽¹⁾⁽²⁾⁽⁴⁾			0.3	V
\|VBIAS-VOFFSET\|	Supply voltage delta (absolute value)⁽¹⁾⁽²⁾⁽⁵⁾			10.5	V
\|VBIAS- VRESET\|	Supply voltage delta (absolute value)⁽¹⁾⁽²⁾⁽⁶⁾			33	V
CLOCK FREQUENCY
f_clock	Clock frequency for low speed interface LS_CLK⁽⁷⁾	108		120	MHz
f_clock	Clock frequency for high-speed interface DCLK ⁽⁸⁾			720	MHz
DCD_IN	Duty cycle distortion	48		52	%
SUBLVDS INTERFACE
\|V_ID\|	LVDS differential input voltage magnitude⁽⁸⁾	150	250	350	mV
V_CM	Common mode voltage⁽⁸⁾	700	900	1100	mV
V_SUBLVDS	SubLVDS voltage⁽⁸⁾	525		1275	mV
Z_LINE	Line differential impedance (PWB/trace)	90	100	110	Ω
Z_IN	Internal differential termination resistance⁽¹⁰⁾	80	100	120	Ω
	100Ω differential PCB trace	6.35		152.4	mm
ENVIRONMENTAL
T_ARRAY	Array temperature, long-term operation⁽⁹⁾⁽¹⁰⁾⁽¹¹⁾⁽¹²⁾	10		40 to 70	°C
T_ARRAY	Array temperature, short-term operation, 500 hr max⁽¹⁰⁾⁽¹³⁾	0		10	°C
T_Window	Window temperature, operational⁽¹⁴⁾			85	°C
\|T_DELTA\|	Absolute Temperature difference between any point on the window edge and the ceramic test point TP1⁽¹⁵⁾			15	°C
T_DP-AVG	Average dew point temperature, (non-condensing)⁽¹⁶⁾			24	°C
T_DP-ELR	Elevated dew point temperature range, (non-condensing)⁽¹⁷⁾		28	36	°C
CT_ELR	Cumulative time in elevated dew point temperature range			6	Months
ILLUMINATION
ILL_UV	Illumination, wavelength < 410nm⁽⁹⁾			10	mW/cm²
ILL_VIS	Illumination power at wavelengths ≥ 410nm and ≤ 800nm⁽¹⁸⁾			20.5	W/cm²
ILL_IR	Illumination, wavelength between > 800nm			10	mW/cm²
ILL_BLU	Illumination power at wavelengths ≥ 410nm and ≤ 475nm⁽¹⁸⁾			6.5	W/cm²
ILL_BLU1	Illumination power at wavelengths ≥ 410nm and ≤ 445nm⁽¹⁸⁾			1.2	W/cm²
ILL_θ	Illumination marginal ray angle⁽¹⁹⁾			55	deg

(1) The following power supplies are all required to operate the DMD: V_DD, V_DDI, V_OFFSET, V_BIAS, and V_RESET. All V_SS connections are required to operate the DMD.

(2) All voltage values are with respect to the V_SS ground pins.

(3) V_OFFSETsupply transients must fall within specified max voltages.

(4) To prevent excess current, the supply voltage delta |V_DDI – V_DD| must be less than the specified limit.

(5) To prevent excess current, the supply voltage delta |V_BIAS – V_OFFSET| must be less than the specified limit.

(6) To prevent excess current, the supply voltage delta |V_BIAS – V_RESET| must be less than the specified limit.

(7) LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.

(8) Refer to the SubLVDS timing requirements in Section 5.8.

(9) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination will reduce device lifetime.

(10) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point (TP1), as shown in Figure 6-1 and the package thermal resistance using Section 6.6.

(11) Per Maximum Recommended Array Temperature—Derating Curve, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Micromirror Landed-On/Landed-Off Duty Cycle for a definition of micromirror landed duty cycle.

(12) Long-term is defined as the usable life of the device.

(13) Short-term is the total cumulative time over the useful life of the device.

(14) Window temperature is the highest temperature on the window edge. The locations of thermal test points TP2, TP3, TP4, and TP5 in Figure 6-1 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, that point should be used.

(15) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge shown in Figure 6-1. The window test points TP2, TP3, TP4, and TP5 shown in Figure 6-1 are intended to result in the worst case delta temperature. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.

(16) The average over time (including storage and operating) that the device is not in the ‘elevated dew point temperature range'.

(17) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CT_ELR.

(18) The maximum allowable optical power incident on the DMD is limited by the maximum optical power density for each wavelength range specified and the micromirror array temperature (T_ARRAY).

(19) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors (POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not been tested or qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM) will contribute to thermal limitations described in this document, and may negatively affect the lifetime.