DLPS273 Data sheet

DLPS273B May 2024 – July 2025 DLP472TE

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

FYW|149
- MCPG035

Thermal pad, mechanical data (Package|Pins)

Orderable Information

5.6 Electrical Characteristics

Over operating free-air temperature range and supply voltages (unless otherwise noted)

PARAMETER⁽¹⁾⁽²⁾		TEST CONDITIONS⁽¹⁾	MIN	TYP	MAX	UNIT
CURRENT – TYPICAL
I_DD	Supply current V_DD⁽³⁾			800	1200	mA
I_DDA	Supply current V_DDA⁽³⁾			1000	1200	mA
I_DDA	Supply current V_DDA⁽³⁾	Single macro mode		500	600	mA
I_OFFSET	Supply current V_OFFSET⁽⁴⁾⁽⁵⁾			20	25	mA
I_BIAS	Supply current V_BIAS⁽⁴⁾⁽⁵⁾			2.5	4.0	mA
I_RESET	Supply current V_RESET⁽⁵⁾		–9.3	–6.9		mA
POWER – TYPICAL
P_DD	Supply power dissipation V_DD⁽³⁾			1440	2437.5	mW
P_DDA	Supply power dissipation V_DDA⁽³⁾			1620	2340	mW
P_DDA	Supply power dissipation V_DDA⁽³⁾	single macro mode		900	1170	mW
P_OFFSET	Supply power dissipation V_OFFSET⁽⁴⁾⁽⁵⁾			230	367.5	mW
P_BIAS	Supply power dissipation V_BIAS⁽⁴⁾⁽⁵⁾			43.2	70.3	mW
P_RESET	Supply power dissipation V_RESET⁽⁵⁾			107.8	152.25	mW
P_TOTAL	Supply power dissipation Total			3441	5367.55	mW
LVCMOS INPUT
I_IL	Low level input current⁽⁶⁾	V_DD = 1.95V, V_I = 0V	–100			nA
I_IH	High level input current⁽⁶⁾	V_DD = 1.95V, V_I = 1.95V			135	µA
LVCMOS OUTPUT
V_OH	DC output high voltage⁽⁷⁾	I_OH = –2mA	0.8 × V_DD			V
V_OL	DC output low voltage⁽⁷⁾	I_OL = 2mA			0.2 × V_DD	V
RECEIVER EYE CHARACTERISTICS
A1	Minimum data eye opening⁽⁸⁾⁽⁹⁾		100		600	mV
A1	Minimum clock eye opening ⁽⁸⁾⁽⁹⁾		295		600	mV
A2	Maximum data signal swing⁽⁸⁾⁽⁹⁾				600	mV
X1	Maximum data eye closure⁽⁸⁾				0.275	UI
X2	Maximum data eye closure⁽⁸⁾				0.4	UI
\| t_DRIFT \|	Drift between Clock and Data between Training Patterns				20	ps
CAPACITANCE
C_IN	Input capacitance LVCMOS	f = 1MHz			10	pF
C_IN	Input capacitance LSIF (low speed interface)	f = 1MHz			20	pF
C_IN	Input capacitance HSSI (high speed serial interface)	f = 1MHz			20	pF
C_OUT	Output capacitance	f = 1MHz			10	pF

(1) All power supply connections are required to operate the DMD: V_DD, V_DDA, V_OFFSET, V_BIAS, and V_RESET. All V_SS connections are required to operate the DMD.

(2) All voltage values are with respect to the ground pins (V_SS).

(3) To prevent excess current, the supply voltage delta | V_DDA – V_DD | must be less than the specified limit.

(4) To prevent excess current, the supply voltage delta | V_BIAS – V_OFFSET | must be less than the specified limit.

(5) Supply power dissipation based on three global resets in 200µs.

(6) LVCMOS input specifications are for pin DMD_DEN_ARSTZ.

(7) LVCMOS output specification is for pins LS_RDATA_A and LS_RDATA_B.

(8) Refer to Figure 5-12, Receiver Eye Mask (1e-12 BER).

(9) Defined in Equation 3 and Equation 4.