DLPS193A November   2020  – July 2022 DLP500YX


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Capacitance at Recommended Operating Conditions
    8. 6.8  Timing Requirements
    9. 6.9  Typical Characteristics
    10. 6.10 System Mounting Interface Loads
    11. 6.11 Micromirror Array Physical Characteristics
    12. 6.12 Micromirror Array Optical Characteristics
    13. 6.13 Window Characteristics
    14. 6.14 Chipset Component Usage Specification
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
      1. 7.6.1 Micromirror Array Temperature Calculation using Illumination Power Density
      2. 7.6.2 Micromirror Array Temperature Calculation using Total Illumination Power
      3. 7.6.3 Micromirror Array Temperature Calculation using Screen Lumens
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 DMD Die Temperature Sensing
  9. Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
    3. 9.3 Restrictions on Hot Plugging and Hot Swapping
      1. 9.3.1 No Hot Plugging
      2. 9.3.2 No Hot Swapping
      3. 9.3.3 Intermittent or Voltage Power Spike Avoidance
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Critical Signal Guidelines
      2. 10.1.2 Power Connection Guidelines
      3. 10.1.3 Noise Coupling Avoidance
    2. 10.2 Layout Example
      1. 10.2.1 Layers
      2. 10.2.2 Impedance Requirements
      3. 10.2.3 Trace Width, Spacing
        1. Voltage Signals
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
      2. 11.2.2 Device Markings
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Timing Requirements

trRise time20% to 80% reference points13V/ns
tfFall time80% to 20% reference points13V/ns
trRise slew rate20% to 80% reference points0.71V/ns
tfFall slew rate80% to 20% reference points0.71V/ns
tCClock cycleDCLK_A, LVDS pair2.5ns
DCLK_B, LVDS pair2.5ns
DCLK_C, LVDS pair2.5ns
DCLK_D, LVDS pair2.5ns
tWPulse durationDCLK_A, LVDS pair1.191.25ns
DCLK_B, LVDS pair1.191.25ns
DCLK_C, LVDS pair1.191.25ns
DCLK_D, LVDS pair1.191.25ns
tSuSetup timeD_A(15:0) before DCLK_A, LVDS pair0.275ns
D_B(15:0) before DCLK_B, LVDS pair0.275ns
D_C(15:0) before DCLK_C, LVDS pair0.275ns
D_D(15:0) before DCLK_D, LVDS pair0.275ns
SCTRL_A before DCLK_A, LVDS pair0.275ns
SCTRL_B before DCLK_B, LVDS pair0.275ns
SCTRL_C before DCLK_C, LVDS pair0.275ns
SCTRL_D before DCLK_D, LVDS pair0.275ns
thHold timeD_A(15:0) after DCLK_A, LVDS pair0.195ns
D_B(15:0) after DCLK_B, LVDS pair0.195ns
D_C(15:0) after DCLK_C, LVDS pair0.195ns
D_D(15:0) after DCLK_D, LVDS pair0.195ns
SCTRL_A after DCLK_A, LVDS pair0.195ns
SCTRL_B after DCLK_B, LVDS pair0.195ns
SCTRL_C after DCLK_C, LVDS pair0.195ns
SCTRL_D after DCLK_D, LVDS pair0.195ns
tSKEWSkew timeChannel B relative to channel A (3)(4)–1.251.25ns
tSKEWSkew timeChannel D relative to channel C(5)(6), LVDS pair–1.251.25ns
See Figure 6-3 for rise time and fall time for SCP.
See Figure 6-5 for timing requirements for LVDS.
Channel A (Bus A) includes the following LVDS pairs: DCLK_AN and DCLK_AP, SCTRL_AN and SCTRL_AP, D_AN(15:0) and D_AP(15:0).
Channel B (Bus B) includes the following LVDS pairs: DCLK_BN and DCLK_BP, SCTRL_BN and SCTRL_BP, D_BN(15:0) and D_BP(15:0).
Channel C (Bus C) includes the following LVDS pairs: DCLK_CN and DCLK_CP, SCTRL_CN and SCTRL_CP, D_CN(15:0) and D_CP(15:0).
Channel D (Bus D) includes the following LVDS pairs: DCLK_DN and DCLK_DP, SCTRL_DN and SCTRL_DP, D_DN(15:0) and D_DP(15:0).
GUID-20201116-CA0I-6CT8-MPG7-H9WZNWQFMPVL-low.gif Figure 6-2 SCP Timing Requirements
See Section 6.4 for fSCPCLK, tSCP_DS, tSCP_DH and tSCP_PD specifications.
SCPCLK falling–edge capture for SCPDI.
SCPCLK rising–edge launch for SCPDO.
See Equation 1
Equation 1. GUID-20201116-CA0I-0CMW-JTQZ-BPZZBKGTJD42-low.gif
GUID-20201116-CA0I-1C9N-ZWNC-MP7VRMSB79RK-low.gif Figure 6-3 SCP Requirements for Rise and Fall

See Section 6.8 for tr and tf specifications and conditions.

GUID-613F4BBD-52E6-47FB-829B-17144F1B170F-low.gif Figure 6-4 Test Load Circuit for Output Propagation Measurement

For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. System designers must use IBIS or other simulation tools to correlate the timing reference load to a system environment.

GUID-20201112-CA0I-FM0K-QZWF-RQRNGTNVZCF6-low.gif Figure 6-5 LVDS Waveform Requirements
Equation 2. GUID-86B70B5E-DEAE-4ED5-B3F9-D4596C9C56FE-low.gif
Equation 3. GUID-CB0A55B8-52F7-4156-BD0E-A21B0595BED6-low.gif

See Section 6.4 for VCM, VID, and VLVDS specifications and conditions.

GUID-20201116-CA0I-MG9X-HKC5-JSD1R8ZVWFRJ-low.gif Figure 6-6 Timing Requirements

GUID-20201112-CA0I-9ZSB-LJLD-S0MBQBR1TTBX-low.gif Figure 6-7 LVDS Interface Channel Skew Definition

See Section 6.8 for timing requirements and LVDS pairs per channel (bus) defining D_P(15:0) and D_N(15:0).