over operating free-air temperature range (unless otherwise noted) (1)
|VCC||Supply voltage for LVCMOS core logic(2)||–0.5||2.3||V|
|VOFFSET||Supply voltage for HVCMOS and micromirror
|VBIAS||Supply voltage for micromirror electrode(2)||–0.5||19||V|
|VRESET||Supply voltage for micromirror electrode(2)||–15||–0.3||V|
||VBIAS – VOFFSET|||Supply voltage difference (absolute value)(4)||11||V|
||VBIAS – VRESET|||Supply voltage difference (absolute value)(5)||34||V|
|Input voltage for all other LVCMOS input pins(2)||–0.5||VCC + 0.5||V|
|Input voltage for all other LVDS input pins (2)(6)||–0.5||VCC + 0.5||V|
||VID|||Input differential voltage (absolute value)(7)||500||mV|
|IID||Input differential current(6)||6.3||mA|
|ƒCLOCK||Clock frequency for LVDS interface, DCLK_A, DCLK_B,
|TARRAY and TWINDOW||Array temperature: operational(8)||0||90||°C|
|Array temperature: non–operational(8)||–40||90||°C|
||TDELTA|||Absolute temperature delta between any point on the
window edge and the ceramic test point TP1 (9)||30||°C|
|TDP||Dew point temperature, operating and non–operating
Stresses beyond those listed under Section 6.1
cause permanent damage to the device. These are stress ratings only, and
functional operation of the device is not implied at these or any other
conditions beyond those indicated under Section 6.4
Exposure above or below the Section 6.4
extended periods may affect device reliability.
(2) All voltages are referenced to common ground VSS. VBIAS, VCC, VOFFSET, and VRESET power supplies are all required for proper DMD operation. VSS must also be connected.
(3) VOFFSET supply transients must fall within specified voltages.
(4) Exceeding the recommended allowable voltage difference between VBIAS and VOFFSET may result in excessive current draw.
(5) Exceeding the recommended allowable voltage difference between VBIAS and VRESET may result in excessive current draw.
(6) LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.
(7) This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.
The highest temperature of the active array (as calculated using Section 7.6
) or of any location along the window edge as defined in Figure 7-2
. The locations of thermal test points TP2, TP3, TP4, and TP5 in Figure 7-2
are intended to measure the highest window edge temperature. If a particular
application causes another location on the window edge to be at a higher
temperature, use that location.
Temperature delta is the highest difference between the ceramic test point 1
(TP1) and anywhere on the window edge as shown in Figure 7-2
. The window test points TP2, TP3, TP4, and TP5 shown in Figure 7-2
are intended to result in the worst case delta. If a particular application
causes another location on the window edge to result in a larger delta temperature,
use that location.