DLPS193 November   2020 DLP500YX

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Capacitance at Recommended Operating Conditions
    8. 6.8  Timing Requirements
    9. 6.9  Typical Characteristics
    10. 6.10 System Mounting Interface Loads
    11. 6.11 Micromirror Array Physical Characteristics
    12. 6.12 Micromirror Array Optical Characteristics
    13. 6.13 Window Characteristics
    14. 6.14 Chipset Component Usage Specification
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
      1. 7.6.1 Micromirror Array Temperature Calculation using Illumination Power Density
      2. 7.6.2 Micromirror Array Temperature Calculation using Total Illumination Power
      3. 7.6.3 Micromirror Array Temperature Calculation using Screen Lumens
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 DMD Die Temperature Sensing
  9. Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
    3. 9.3 Restrictions on Hot Plugging and Hot Swapping
      1. 9.3.1 No Hot Plugging
      2. 9.3.2 No Hot Swapping
      3. 9.3.3 Intermittent or Voltage Power Spike Avoidance
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Critical Signal Guidelines
      2. 10.1.2 Power Connection Guidelines
      3. 10.1.3 Noise Coupling Avoidance
    2. 10.2 Layout Example
      1. 10.2.1 Layers
      2. 10.2.2 Impedance Requirements
      3. 10.2.3 Trace Width, Spacing
        1. 10.2.3.1 Voltage Signals
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MINMAXUNIT
SUPPLY VOLTAGES
VCCSupply voltage for LVCMOS core logic(2)–0.52.3V
VOFFSETSupply voltage for HVCMOS and micromirror electrode(2)(3)–0.511V
VBIASSupply voltage for micromirror electrode(2)–0.519V
VRESETSupply voltage for micromirror electrode(2)–15–0.3V
|VBIAS – VOFFSET|Supply voltage difference (absolute value)(4)11V
|VBIAS – VRESET|Supply voltage difference (absolute value)(5)34V
INPUT VOLTAGES
Input voltage for all other LVCMOS input pins(2)–0.5VCC + 0.5V
Input voltage for all other LVDS input pins (2)(6)–0.5VCC + 0.5V
|VID|Input differential voltage (absolute value)(7)500mV
IIDInput differential current(6)6.3mA
CLOCKS
ƒCLOCKClock frequency for LVDS interface, DCLK_A, DCLK_B, DCLK_C, DCLK_D400MHz
ENVIRONMENTAL
TARRAY and TWINDOWArray temperature: operational(8)090°C
Array temperature: non–operational(8)–4090°C
|TDELTA|Absolute temperature delta between any point on the window edge and the ceramic test point TP1 (9)30°C
TDPDew point temperature, operating and non–operating (non-condensing)81°C
Stresses beyond those listed under Section 6.1 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Section 6.4. Exposure above or below the Section 6.4 for extended periods may affect device reliability.
All voltages are referenced to common ground VSS. VBIAS, VCC, VOFFSET, and VRESET power supplies are all required for proper DMD operation. VSS must also be connected.
VOFFSET supply transients must fall within specified voltages.
Exceeding the recommended allowable voltage difference between VBIAS and VOFFSET may result in excessive current draw.
Exceeding the recommended allowable voltage difference between VBIAS and VRESET may result in excessive current draw.
LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.
This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.
The highest temperature of the active array (as calculated using Section 7.6) or of any location along the window edge as defined in Figure 7-2. The locations of thermal test points TP2, TP3, TP4, and TP5 in Figure 7-2 are intended to measure the highest window edge temperature. If a particular application causes another location on the window edge to be at a higher temperature, use that location.
Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in Figure 7-2. The window test points TP2, TP3, TP4, and TP5 shown in Figure 7-2 are intended to result in the worst case delta. If a particular application causes another location on the window edge to result in a larger delta temperature, use that location.