DLPS193A Data sheet

DLPS193A November 2020 – July 2022 DLP500YX

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

FXK|257
- MCLG042

Thermal pad, mechanical data (Package|Pins)

Orderable Information

dlps193a_oa

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is implied when operating the device above or below these limits.

		MIN	NOM	MAX	UNIT
VOLTAGE SUPPLY
V_CC	LVCMOS logic supply voltage⁽¹⁾	1.65	1.8	1.95	V
V_OFFSET	Mirror electrode and HVCMOS voltage⁽¹⁾⁽²⁾	9.5	10	10.5	V
V_BIAS	Mirror electrode voltage⁽¹⁾	17.5	18	18.5	V
V_RESET	Mirror electrode voltage⁽¹⁾	–14.5	–14	–13.5	V
\|V_BIAS – V_OFFSET\|	Supply voltage difference (absolute value)⁽³⁾			10.5	V
\|V_BIAS – V_RESET\|	Supply voltage difference (absolute value)⁽⁴⁾			33	V
LVCMOS INTERFACE
V_IH(DC)	DC input high voltage⁽⁵⁾	0.7 × V_CC		V_CC + 0.3	V
V_IL(DC)	DC input low voltage⁽⁵⁾	–0.3		0.3 × V_CC	V
V_IH(AC)	AC input high voltage⁽⁵⁾	0.8 × V_CC		V_CC + 0.3	V
V_IL(AC)	AC input low voltage⁽⁵⁾	–0.3		0.2 × V_CC	V
t_PWRDNZ	PWRDNZ pulse duration⁽⁶⁾	10			ns
SCP INTERFACE
ƒ_SCPCLK	SCP clock frequency⁽⁷⁾			500	kHz
t_{SCP_PD}	Propagation delay, clock to Q, from rising-edge of SCPCLK to valid SCPDO⁽⁸⁾	0		900	ns
t_{SCP_NEG_ENZ}	Time between falling-edge of SCPENZ and the first rising-edge of SCPCLK	1			µs
t_{SCP_POS_ENZ}	Time between falling-edge of SCPCLK and the rising-edge of SCPENZ	1			µs
t_{SCP_DS}	SCPDI clock setup time (before SCPCLK falling edge)⁽⁸⁾	800			ns
t_{SCP_DH}	SCPDI hold time (after SCPCLK falling edge)⁽⁸⁾	900			ns
t_{SCP_PW_ENZ}	SCPENZ inactive pulse duration (high level)	2			µs
LVDS INTERFACE
ƒ_CLOCK	Clock frequency for LVDS interface (all channels), DCLK⁽⁹⁾			400	MHz
\|V_ID\|	Input differential voltage (absolute value)⁽¹⁰⁾	150	300	440	mV
V_CM	Common mode voltage⁽¹⁰⁾	1100	1200	1300	mV
V_LVDS	LVDS voltage⁽¹⁰⁾	880		1520	mV
t_{LVDS_RSTZ}	Time required for LVDS receivers to recover from PWRDNZ			2000	ns
Z_IN	Internal differential termination resistance	80	100	120	Ω
Z_LINE	Line differential impedance (PWB/trace)	90	100	110	Ω
ENVIRONMENTAL
T_ARRAY	Array temperature, long–term operational⁽¹¹⁾⁽¹²⁾⁽¹³⁾⁽¹⁴⁾	10		40 to 70⁽¹³⁾	°C
T_ARRAY	Array temperature, short–term operational⁽¹²⁾⁽¹⁵⁾	0		10	°C
T_WINDOW	Window temperature – operational⁽¹⁶⁾			85	°C
\|T_DELTA\|	Absolute temperature delta between any point on the window edge and the ceramic test point TP1⁽¹⁶⁾⁽¹⁷⁾			14	°C
T_DP-AVG	Average dew point temperature (non-condensing)⁽¹⁸⁾			28	°C
T_DP-ELR	Elevated dew point temperature range (non-condensing)⁽¹⁹⁾	28		36	°C
CT_ELR	Cumulative time in elevated dew point temperature range			24	Months
ILL_θ	Illumination marginal ray angle⁽²⁰⁾			55	deg
For Illumination Source Between 420 nm and 700 nm
ILL_VIS	Illumination power density on array⁽²¹⁾			31	W/cm²
ILL_VISTP	Illumination total power on array			22	W
For Illumination Source <420 nm and >700 nm
ILL_IR	Illumination wavelengths > 700 nm			10	mW/cm²
ILL_UV	Illumination wavelengths < 420 nm⁽¹¹⁾			10	mW/cm²

(1) All voltages are referenced to common ground V_SS. V_BIAS, V_CC, V_OFFSET, and V_RESET power supplies are all required for proper DMD operation. V_SS must also be connected.

(2) V_OFFSET supply transients must fall within specified max voltages.

(3) To prevent excess current, the supply voltage difference |V_BIAS – V_OFFSET| must be less than the specified limit. See Section 9, Figure 9-1, and Table 9-1.

(4) To prevent excess current, the supply voltage difference |V_BIAS – V_RESET| must be less than the specified limit. See Section 9, Figure 9-1, and Table 9-1.

(5) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, “Low-Power Double Data Rate (LPDDR)” JESD209B. Tester conditions for V_IH and V_IL.

Frequency = 60 MHz. Maximum rise time = 2.5 ns at 20/80
Frequency = 60 MHz. Maximum fall time = 2.5 ns at 80/20

(6) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tristates the SCPDO output pin.

(7) The SCP clock is a gated clock. Duty cycle must be 50% ± 10%. SCP parameter is related to the frequency of DCLK.

(8) See Figure 6-2.

(9) See LVDS timing requirements in Section 6.8 and Figure 6-6.

(10) See LVDS waveform requirements in Figure 6-5.

(11) Simultaneous exposure of the DMD to the maximum Section 6.4 for temperature and UV illumination reduces device lifetime.

(12) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1) shown in Figure 7-2 and the package thermal resistance Section 7.6.

(13) Per Figure 6-1, the maximum operational array temperature must be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. See Section 7.7 for a definition of micromirror landed duty cycle.

(14) Long-term is defined as the usable life of the device.

(15) Array temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up). Short-term is defined as the cumulative time over the usable life of the device and is less than 500 hours.

(16) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in Figure 7-2. The window test points TP2, TP3, TP4, and TP5 shown in Figure 7-2 are intended to result in the worst case delta temperature. If a particular application causes another location on the window edge to result in a larger delta in temperature, use that location.

(17) DMD is qualified at the maximum temperature specified. Operation of the DMD outside of these limits has not been tested.

(18) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(19) Limit exposure to dew point temperatures in the elevated range during storage and operation to less than a total cumulative time of CT_ELR.

(20) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including the pond of micromirrors (POM), cannot exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM) contributes to thermal limitations described in this document, and may negatively affect lifetime.

(21) The maximum optical power that can be incident on the DMD is limited by the maximum optical power density and the micromirror array temperature.

Figure 6-1 Maximum Recommended Array Temperature—Derating Curve