DLPS193 November   2020 DLP500YX

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Capacitance at Recommended Operating Conditions
    8. 6.8  Timing Requirements
    9. 6.9  Typical Characteristics
    10. 6.10 System Mounting Interface Loads
    11. 6.11 Micromirror Array Physical Characteristics
    12. 6.12 Micromirror Array Optical Characteristics
    13. 6.13 Window Characteristics
    14. 6.14 Chipset Component Usage Specification
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
      1. 7.6.1 Micromirror Array Temperature Calculation using Illumination Power Density
      2. 7.6.2 Micromirror Array Temperature Calculation using Total Illumination Power
      3. 7.6.3 Micromirror Array Temperature Calculation using Screen Lumens
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 DMD Die Temperature Sensing
  9. Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
    3. 9.3 Restrictions on Hot Plugging and Hot Swapping
      1. 9.3.1 No Hot Plugging
      2. 9.3.2 No Hot Swapping
      3. 9.3.3 Intermittent or Voltage Power Spike Avoidance
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Critical Signal Guidelines
      2. 10.1.2 Power Connection Guidelines
      3. 10.1.3 Noise Coupling Avoidance
    2. 10.2 Layout Example
      1. 10.2.1 Layers
      2. 10.2.2 Impedance Requirements
      3. 10.2.3 Trace Width, Spacing
        1. 10.2.3.1 Voltage Signals
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is implied when operating the device above or below these limits.
MINNOMMAXUNIT
VOLTAGE SUPPLY
VCCLVCMOS logic supply voltage(1)1.651.81.95V
VOFFSETMirror electrode and HVCMOS voltage(1)(2)9.51010.5V
VBIASMirror electrode voltage(1)17.51818.5V
VRESETMirror electrode voltage(1)–14.5–14–13.5V
|VBIAS – VOFFSET|Supply voltage difference (absolute value)(3)10.5V
|VBIAS – VRESET|Supply voltage difference (absolute value)(4)33V
LVCMOS INTERFACE
VIH(DC)DC input high voltage(5)0.7 × VCCVCC + 0.3V
VIL(DC)DC input low voltage(5)–0.30.3 × VCCV
VIH(AC)AC input high voltage(5)0.8 × VCCVCC + 0.3V
VIL(AC)AC input low voltage(5)–0.30.2 × VCCV
tPWRDNZPWRDNZ pulse duration(6)10ns
SCP INTERFACE
ƒSCPCLKSCP clock frequency(7)500kHz
tSCP_PDPropagation delay, clock to Q, from rising-edge of SCPCLK to valid SCPDO(8)0900ns
tSCP_NEG_ENZTime between falling-edge of SCPENZ and the first rising-edge of SCPCLK1µs
tSCP_POS_ENZTime between falling-edge of SCPCLK and the rising-edge of SCPENZ1µs
tSCP_DSSCPDI clock setup time (before SCPCLK falling edge)(8)800ns
tSCP_DHSCPDI hold time (after SCPCLK falling edge)(8)900ns
tSCP_PW_ENZSCPENZ inactive pulse duration (high level)2µs
LVDS INTERFACE
ƒCLOCKClock frequency for LVDS interface (all channels), DCLK(9)400MHz
|VID|Input differential voltage (absolute value)(10)150300440mV
VCMCommon mode voltage(10)110012001300mV
VLVDSLVDS voltage(10)8801520mV
tLVDS_RSTZTime required for LVDS receivers to recover from PWRDNZ2000ns
ZINInternal differential termination resistance80100120Ω
ZLINELine differential impedance (PWB/trace)90100110Ω
ENVIRONMENTAL
TARRAYArray temperature, long–term operational(11)(12)(13)(14)1040 to 70(13)°C
Array temperature, short–term operational(12)(15)010°C
TWINDOWWindow temperature – operational(16)85°C
|TDELTA|Absolute temperature delta between any point on the window edge and the ceramic test point TP1(16)(17)14°C
TDP-AVGAverage dew point temperature (non-condensing)(18)28°C
TDP-ELRElevated dew point temperature range (non-condensing)(19)2836°C
CTELRCumulative time in elevated dew point temperature range24Months
ILLθIllumination marginal ray angle(20)55deg
For Illumination Source Between 420 nm and 700 nm
ILLVISIllumination power density on array(21)31W/cm2
ILLVISTPIllumination total power on array22W
For Illumination Source <420 nm and >700 nm
ILLIRIllumination wavelengths > 700 nm10mW/cm2
ILLUVIllumination wavelengths < 420 nm(11)10mW/cm2
All voltages are referenced to common ground VSS. VBIAS, VCC, VOFFSET, and VRESET power supplies are all required for proper DMD operation. VSS must also be connected.
VOFFSET supply transients must fall within specified max voltages.
To prevent excess current, the supply voltage difference |VBIAS – VOFFSET| must be less than the specified limit. See Section 9, Figure 9-1, and Table 9-1.
To prevent excess current, the supply voltage difference |VBIAS – VRESET| must be less than the specified limit. See Section 9, Figure 9-1, and Table 9-1.
Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, “Low-Power Double Data Rate (LPDDR)” JESD209B. Tester conditions for VIH and VIL.
  • Frequency = 60 MHz. Maximum rise time = 2.5 ns at 20/80
  • Frequency = 60 MHz. Maximum fall time = 2.5 ns at 80/20
PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tristates the SCPDO output pin.
The SCP clock is a gated clock. Duty cycle must be 50% ± 10%. SCP parameter is related to the frequency of DCLK.
See Figure 6-2.
See LVDS timing requirements in Section 6.8 and Figure 6-6.
See LVDS waveform requirements in Figure 6-5.
Simultaneous exposure of the DMD to the maximum Section 6.4 for temperature and UV illumination reduces device lifetime.
The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1) shown in Figure 7-2 and the package thermal resistance Section 7.6.
Per Figure 6-1, the maximum operational array temperature must be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. See Section 7.7 for a definition of micromirror landed duty cycle.
Long-term is defined as the usable life of the device.
Array temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up). Short-term is defined as the cumulative time over the usable life of the device and is less than 500 hours.
Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in Figure 7-2. The window test points TP2, TP3, TP4, and TP5 shown in Figure 7-2 are intended to result in the worst case delta temperature. If a particular application causes another location on the window edge to result in a larger delta in temperature, use that location.
DMD is qualified at the maximum temperature specified. Operation of the DMD outside of these limits has not been tested.
The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
Limit exposure to dew point temperatures in the elevated range during storage and operation to less than a total cumulative time of CTELR.
The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including the pond of micromirrors (POM), cannot exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM) contributes to thermal limitations described in this document, and may negatively affect lifetime.
The maximum optical power that can be incident on the DMD is limited by the maximum optical power density and the micromirror array temperature.
GUID-96060CB1-2F11-4D59-9BF0-008B0D1BDB3F-low.gifFigure 6-1 Maximum Recommended Array Temperature - Derating Curve