DLPS193 November   2020 DLP500YX

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Capacitance at Recommended Operating Conditions
    8. 6.8  Timing Requirements
    9. 6.9  Typical Characteristics
    10. 6.10 System Mounting Interface Loads
    11. 6.11 Micromirror Array Physical Characteristics
    12. 6.12 Micromirror Array Optical Characteristics
    13. 6.13 Window Characteristics
    14. 6.14 Chipset Component Usage Specification
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
      1. 7.6.1 Micromirror Array Temperature Calculation using Illumination Power Density
      2. 7.6.2 Micromirror Array Temperature Calculation using Total Illumination Power
      3. 7.6.3 Micromirror Array Temperature Calculation using Screen Lumens
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 DMD Die Temperature Sensing
  9. Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
    3. 9.3 Restrictions on Hot Plugging and Hot Swapping
      1. 9.3.1 No Hot Plugging
      2. 9.3.2 No Hot Swapping
      3. 9.3.3 Intermittent or Voltage Power Spike Avoidance
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Critical Signal Guidelines
      2. 10.1.2 Power Connection Guidelines
      3. 10.1.3 Noise Coupling Avoidance
    2. 10.2 Layout Example
      1. 10.2.1 Layers
      2. 10.2.2 Impedance Requirements
      3. 10.2.3 Trace Width, Spacing
        1. 10.2.3.1 Voltage Signals
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Intermittent or Voltage Power Spike Avoidance

When DMD power and/or data and clock inputs are energized, twisting of the DMD, DMD socket, or DMD board must be avoided when trying to align the DMD within an optical engine. This twisting motion can create power intermittences and/or voltage spikes exceeding input power and data specifications of the DMD which may ultimately affect the DMD reliability. PCB power/data/clock/control circuits must be de-energized before making or removing connections, including cables, connectors, probes and bed-of-nails connections.

PCB and System design considerations must take into account ways to prevent external influence of DMD input power clock, data and control signals. Robust connectors must be used which are resistant to intermittent connections or noise spikes if jostled or vibrated. Connectors must be used which are rated to exceed the number of insertion/removal cycles expected in the application. External electromagnetic emitters must not be placed nearby these sensitive circuits unless adequate EMI shielding is properly used. Sufficient bulk decoupling and component decoupling capacitance as well as appropriate PCB layout techniques must be available for all electrical components within the DMD based "system" such that ground bounce does not occur. See the section on Section 10.1 for more layout information.