DLPS013G April   2010  – January 2019 DLP5500


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application Schematic
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Storage Conditions
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  Timing Requirements
    8. 7.8  System Mounting Interface Loads
    9. 7.9  Micromirror Array Physical Characteristics
    10. 7.10 Micromirror Array Optical Characteristics
    11. 7.11 Window Characteristics
    12. 7.12 Chipset Component Usage Specification
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Video Modes
      2. 8.4.2 Structured Light Modes
        1. Static Image Buffer Mode
        2. Real Time Structured Light Mode
    5. 8.5 Window Characteristics and Optics
      1. 8.5.1 Optical Interface and System Image Quality
      2. 8.5.2 Numerical Aperture and Stray Light Control
      3. 8.5.3 Pupil Match
      4. 8.5.4 Illumination Overfill
    6. 8.6 Micromirror Array Temperature Calculation
      1. 8.6.1 Package Thermal Resistance
      2. 8.6.2 Case Temperature
      3. 8.6.3 Micromirror Array Temperature Calculation for Uniform Illumination
    7. 8.7 Micromirror Landed-on/Landed-Off Duty Cycle
      1. 8.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 8.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 8.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 8.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. DLP5500 System Interface
  10. 10Power Supply Recommendations
    1. 10.1 DMD Power-Up and Power-Down Procedures
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Impedance Requirements
      2. 11.1.2 PCB Signal Routing
      3. 11.1.3 Fiducials
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Documentation
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Feature Description

The DLP5500 device consists of 786,432 highly reflective, digitally switchable, micrometer-sized mirrors (micromirrors) organized in a two-dimensional orthogonal pixel array. Refer to Figure 11 and Figure 14.

Each aluminum micromirror is switchable between two discrete angular positions, –a and +a. The angular positions are measured relative to the micromirror array plane, which is parallel to the silicon substrate. Refer to Micromirror Array Optical Characteristics and Figure 15.

The parked position of the micromirror is not a latched position and is therefore not necessarily perfectly parallel to the array plane. Individual micromirror flat state angular positions may vary. Tilt direction of the micromirror is perpendicular to the hinge-axis. The on-state landed position is directed toward the left-top edge of the package, as shown in Figure 14.

Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell contents, after the mirror clocking pulse is applied. The angular position (–a and +a) of the individual micromirrors changes synchronously with a micromirror clocking pulse, rather than being coincident with the CMOS memory cell data update.

Writing logic 1 into a memory cell followed by a mirror clocking pulse results in the corresponding micromirror switching to the +a position. Writing logic 0 into a memory cell followed by a mirror clocking pulse results in the corresponding micromirror switching to the – a position.

Updating the angular position of the micromirror array consists of two steps. First, update the contents of the CMOS memory. Second, apply a micromirror clocking pulse (reset) to all or a portion of the micromirror array (depending upon the configuration of the system). Micromirror reset pulses are generated externally by the DLPC200 controller in conjunction with the DLPA200 analog driver, with application of the pulses being coordinated by the DLPC200 controller.

For more information, see the TI application report DLPA008, DMD101: Introduction to Digital Micromirror Device (DMD) Technology.

DLP5500 Micromirror_Array_Pitch_Hinge_Axis.gif
Refer to Figure 11 and Figure 12.
Figure 14. Micromirror Array, Pitch, Hinge Axis Orientation
DLP5500 Micromirror_States_On_Off_Flat.gif
Micromirror States: On, Off, Flat
Figure 15. Micromirror States: On, Off, Flat