DLPS073F March   2016  – May 2019 DLP5530-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      DLP5530-Q1 DLP Chipset System Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions – Connector Pins
    2.     Pin Functions – Test Pads
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sub-LVDS Data Interface
      2. 7.3.2 Low Speed Interface for Control
      3. 7.3.3 DMD Voltage Supplies
      4. 7.3.4 Asynchronous Reset
      5. 7.3.5 Temperature Sensing Diode
        1. 7.3.5.1 Temperature Sense Diode Theory
    4. 7.4 System Optical Considerations
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill
    5. 7.5 DMD Image Performance Specification
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application Overview
      2. 8.2.2 Reference Design
      3. 8.2.3 Application Mission Profile Consideration
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 DMD Handling
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • FYK|149
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

FYK Package
149-Pin CPGA
Bottom View
DLP5530-Q1 auto_g2_pins.gif

Pin Functions – Connector Pins

PIN TYPE SIGNAL DATA RATE DESCRIPTION
NAME NO.
DATA INPUTS
D_AN(0) L2 I SubLVDS Double Data, Negative
D_AN(1) K2 I SubLVDS Double Data, Negative
D_AN(2) J2 I SubLVDS Double Data, Negative
D_AN(3) H2 I SubLVDS Double Data, Negative
D_AN(4) F2 I SubLVDS Double Data, Negative
D_AN(5) E2 I SubLVDS Double Data, Negative
D_AN(6) D2 I SubLVDS Double Data, Negative
D_AN(7) C2 I SubLVDS Double Data, Negative
D_AP(0) L1 I SubLVDS Double Data, Positive
D_AP(1) K1 I SubLVDS Double Data, Positive
D_AP(2) J1 I SubLVDS Double Data, Positive
D_AP(3) H1 I SubLVDS Double Data, Positive
D_AP(4) F1 I SubLVDS Double Data, Positive
D_AP(5) E1 I SubLVDS Double Data, Positive
D_AP(6) D1 I SubLVDS Double Data, Positive
D_AP(7) C1 I SubLVDS Double Data, Positive
D_BN(0) K19 I SubLVDS Double Data, Negative
D_BN(1) J19 I SubLVDS Double Data, Negative
D_BN(2) H19 I SubLVDS Double Data, Negative
D_BN(3) G19 I SubLVDS Double Data, Negative
D_BN(4) E19 I SubLVDS Double Data, Negative
D_BN(5) D19 I SubLVDS Double Data, Negative
D_BN(6) C19 I SubLVDS Double Data, Negative
D_BN(7) B19 I SubLVDS Double Data, Negative
D_BP(0) K20 I SubLVDS Double Data, Positive
D_BP(1) J20 I SubLVDS Double Data, Positive
D_BP(2) H20 I SubLVDS Double Data, Positive
D_BP(3) G20 I SubLVDS Double Data, Positive
D_BP(4) E20 I SubLVDS Double Data, Positive
D_BP(5) D20 I SubLVDS Double Data, Positive
D_BP(6) C20 I SubLVDS Double Data, Positive
D_BP(7) B20 I SubLVDS Double Data, Positive
DCLK_AN G2 I SubLVDS Double Clock, Negative
DCLK_AP G1 I SubLVDS Double Clock, Positive
DCLK_BN F19 I SubLVDS Double Clock, Negative
DCLK_BP F20 I SubLVDS Double Clock, Positive
LS_CLKN R3 I SubLVDS Single Clock for Low Speed Interface, Negative
LS_CLKP T3 I SubLVDS Single Clock for Low Speed Interface, Positive
LS_WDATAN R2 I SubLVDS Single Write Data for Low Speed Interface, Negative
LS_WDATAP T2 I SubLVDS Single Write Data for Low Speed Interface, Positive
CONTROL INPUTS
DMD_DEN_ARSTZ T10 I LPSDR Asynchronous Reset Active Low. Logic High Enables DMD.
LS_RDATA_A T5 O LPSDR Single Read Data for Low Speed Interface
LS_RDATA_B T6 O LPSDR Single Read Data for Low Speed Interface
TEMPERATURE SENSE DIODE
TEMP_N P1 O Calibrated temperature diode used to assist accurate temperature measurements of DMD die.
TEMP_P N1 I
RESERVED PINS
VCCH A8 Ground Reserved Pin. Connect to Ground.
VCCH A9 Ground
VCCH A10 Ground
VCCH B8 Ground
VCCH B9 Ground
VCCH B10 Ground
VSSH A11 Ground Reserved Pin. Connect to Ground.
VSSH A12 Ground
VSSH A13 Ground
VSSH B11 Ground
VSSH B12 Ground
VSSH B13 Ground
POWER
VBIAS T7 Power Supply voltage for positive bias level at micromirrors.
VBIAS T15 Power
VOFFSET T9 Power Supply voltage for High Voltage CMOS core logic. Supply voltage for offset level at micromirrors
VOFFSET T13 Power
VOFFSET A5 Power
VOFFSET B5 Power
VOFFSET A16 Power
VOFFSET B16 Power
VRESET T8 Power Supply voltage for negative reset level at micromirrors.
VRESET T14 Power
VDD R4 Power Supply voltage for Low Voltage CMOS core logic; for LPSDR inputs; for normal high level at micromirror address electrodes.
VDD R10 Power
VDD R11 Power
VDD R20 Power
VDD N2 Power
VDD M20 Power
VDD L3 Power
VDD K18 Power
VDD H3 Power
VDD G18 Power
VDD E3 Power
VDD D18 Power
VDD C3 Power
VDD A6 Power
VDD A18 Power
VDDI T4 Power Supply voltage for SubLVDS receivers.
VDDI R1 Power
VDDI M3 Power
VDDI L18 Power
VDDI J3 Power
VDDI H18 Power
VDDI F3 Power
VDDI E18 Power
VDDI B3 Power
VDDI B18 Power
VSS T1 Ground Common return. Ground for all power.
VSS T16 Ground
VSS T19 Ground
VSS T20 Ground
VSS R5 Ground
VSS R6 Ground
VSS R7 Ground
VSS R8 Ground
VSS R9 Ground
VSS R13 Ground
VSS R14 Ground
VSS R15 Ground
VSS P2 Ground
VSS P3 Ground
VSS P20 Ground
VSS N19 Ground
VSS N20 Ground
VSS M1 Ground
VSS M2 Ground
VSS L19 Ground
VSS L20 Ground
VSS K3 Ground
VSS J18 Ground
VSS G3 Ground
VSS F18 Ground
VSS D3 Ground
VSS C18 Ground
VSS B2 Ground
VSS B4 Ground
VSS B15 Ground
VSS B17 Ground
VSS A3 Ground
VSS A4 Ground
VSS A7 Ground
VSS A15 Ground
VSS A17 Ground
VSS A19 Ground
VSS A20 Ground

Pin Functions – Test Pads

NUMBER SYSTEM BOARD
T11 Do not connect
T12 Do not connect
T17 Do not connect
T18 Do not connect
R12 Do not connect
R16 Do not connect
R17 Do not connect
R18 Do not connect
R19 Do not connect
P18 Do not connect
P19 Do not connect
N3 Do not connect
N18 Do not connect
M18 Do not connect
M19 Do not connect
B6 Do not connect
B7 Do not connect
B14 Do not connect
A14 Do not connect