DLPS200B July   2020  – April 2021 DLP5530S-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5.     Illumination Overfill Diagram
    6. 6.5  Thermal Information
    7. 6.6  Electrical Characteristics
    8. 6.7  Timing Requirements
    9.     Electrical and Timing Diagrams
    10. 6.8  Switching Characteristics
    11.     LPSDR and Test Load Circuit Diagrams
    12. 6.9  System Mounting Interface Loads
    13.     System Interface Loads Diagram
    14. 6.10 Physical Characteristics of the Micromirror Array
    15.     Array Physical Characteristics Diagram
    16. 6.11 Micromirror Array Optical Characteristics
    17. 6.12 Window Characteristics
    18. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sub-LVDS Data Interface
      2. 7.3.2 Low Speed Interface for Control
      3. 7.3.3 DMD Voltage Supplies
      4. 7.3.4 Asynchronous Reset
      5. 7.3.5 Temperature Sensing Diode
        1. 7.3.5.1 Temperature Sense Diode Theory
    4. 7.4 System Optical Considerations
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill
    5. 7.5 DMD Image Performance Specification
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application Overview
      2. 8.2.2 Reference Design
      3. 8.2.3 Application Mission Profile Consideration
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 DMD Handling
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • FYS|149
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1 Application Overview

Figure 8-1 shows the system block diagram for a DLP HUD system. The system uses the DLPC230S-Q1, TPS99000S-Q1, and the DLP5530S-Q1 automotive DMD to enable a head-up display with high brightness, high efficiency, and a large virtual image distance. The combination of the DLPC230S-Q1 and TPS99000S-Q1 removes the need for external SDRAM and a dedicated microprocessor. The chipset manages the illumination control of LED sources, power sequencing functions, and system management functions. Additionally, the chipset supports numerous system diagnostic and built-in self test (BIST) features. The following paragraphs describe the functionality of the chipset used for a HUD system in more detail.

The DLPC230S-Q1 is a controller for the DMD and the light sources in the DLP HUD module. It receives input video from the host and synchronizes DMD and light source timing in order to achieve the desired video. The DLPC230S-Q1 formats input video data that is displayed on the DMD. It synchronizes these video segments with light source timing in order to create a video with a multi-colored display.

The DLPC230S-Q1 receives inputs from a host processor in the vehicle. The host provides commands and input video data. Host commands can be sent using either the I2C bus or SPI bus. The bus that is not being used for host commands can be used as a read-only bus for diagnostic purposes. Input video can be sent over an OpenLDI bus or a parallel 24-bit bus. The SPI flash memory provides the embedded software for the DLPC230S-Q1’s ARM core and default settings. The TPS99000S-Q1 provides diagnostic and monitoring information to the DLPC230S-Q1 using an SPI bus and several other control signals such as PARKZ, INTZ, and RESETZ to manage power-up and power-down sequencing. The TMP411 uses an I2C interface to provide the DMD array temperature to the DLPC230S-Q1.

The outputs of the DLPC230S-Q1 are configuration and monitoring commands to the TPS99000S-Q1, timing controls to the LED or laser driver, control and data signals to the DMD, and monitoring and diagnostics information to the host processor. The DLPC230S-Q1 communicates with the TPS99000S-Q1 over an SPI bus. It uses this to configure the TPS99000S-Q1 and to read monitoring and diagnostics information from the TPS99000S-Q1. The DLPC230S-Q1 sends drive enable signals to the LED or laser driver, and synchronizes this with the DMD mirror timing. The control signals to the DMD are sent using a sub-LVDS interface.

The TPS99000S-Q1 is a highly integrated mixed-signal IC that controls DMD power and provides monitoring and diagnostics information for the DLP HUD system. The power sequencing and monitoring blocks of the TPS99000S-Q1 properly power up the DMD and provide accurate DMD voltage rails (–16 V, 8.5 V, and 10 V), and then monitor the system’s power rails during operation. The integration of these functions into one IC significantly reduces design time and complexity. The TPS99000S-Q1 also has several output signals that can be used to control a variety of LED or laser driver topologies. The TPS99000S-Q1 has several general-purpose ADCs that designers can use for system level monitoring, such as over-brightness detection.

The TPS99000S-Q1 receives inputs from the DLPC230S-Q1, the power rails it monitors, the host processor, and potentially several other ADC ports. The DLPC230S-Q1 sends configuration and control commands to the TPS99000S-Q1 over an SPI bus and several other control signals. The DLPC230S-Q1’s clocks are also monitored by the watchdogs in the TPS99000S-Q1 to detect any errors. The power rails are monitored by the TPS99000S-Q1 in order to detect power failures or glitches and request a proper power down of the DMD in case of an error. The host processor can read diagnostics information from the TPS99000S-Q1 using a dedicated SPI bus, which enables independent monitoring. Additionally the host can request the image to be turned on or off using a PROJ_ON signal. Lastly, the TPS99000S-Q1 has several general-purpose ADCs that can be used to implement system level monitoring functions.

The outputs of the TPS99000S-Q1 are diagnostic information and error alerts to the DLPC230S-Q1, and control signals to the LED or laser driver. The TPS99000S-Q1 can output diagnostic information to the host and the DLPC230S-Q1 over two SPI buses. In case of critical system errors, such as power loss, it outputs signals to the DLPC230S-Q1 that trigger power down or reset sequences. It also has output signals that can be used to implement various LED or laser driver topologies.

The DMD is a micro-electro-mechanical system (MEMS) device that receives electrical signals as an input (video data), and produces a mechanical output (mirror position). The electrical interface to the DMD is a sub-LVDS interface with the DLPC230S-Q1. The mechanical output is the state of more than 1.3 million mirrors in the DMD array that can be tilted ±12°. In a projection system the mirrors are used as pixels in order to display an image.