DLPS075G April   2016  – May 2019 DLP5531-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      DLP5531-Q1 DLP Chipset System Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions – Connector Pins
    2.     Pin Functions – Test Pads
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sub-LVDS Data Interface
      2. 7.3.2 Low Speed Interface for Control
      3. 7.3.3 DMD Voltage Supplies
      4. 7.3.4 Asynchronous Reset
      5. 7.3.5 Temperature Sensing Diode
        1. 7.3.5.1 Temperature Sense Diode Theory
    4. 7.4 System Optical Considerations
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill
    5. 7.5 DMD Image Performance Specification
    6. 7.6 Micromirror Array Temperature Calculation
      1. 7.6.1 Temperature Rise Through the Package for Heatsink Design
      2. 7.6.2 Monitoring Array Temperature Using the Temperature Sense Diode
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application Overview
      2. 8.2.2 Reference Design
      3. 8.2.3 Application Mission Profile Consideration
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 DMD Handling
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • FYK|149
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS(2) MIN TYP(10) MAX UNIT
CURRENT
IDD Supply current: VDD(3)(4) VDD = 1.95 V 369 mA
VDD = 1.8 V
IDDI Supply current: VDDI(3)(4) VDDI = 1.95 V 62 mA
VDD = 1.8 V
IOFFSET Supply current: VOFFSET(5) VOFFSET = 8.75 V 16.1 mA
VOFFSET = 8.5 V
IBIAS Supply current: VBIAS(5) VBIAS = 16.5 V 1.3 mA
VBIAS = 16 V
IRESET Supply current: VRESET VRESET = –10.5 V –10.2 mA
VRESET = –10 V
POWER(9)
PDD Supply power dissipation: VDD(3)(4) VDD = 1.95 V 720 mW
VDD = 1.8 V
PDDI Supply power dissipation: VDDI(3)(4) VDDI = 1.95 V 121 mW
VDD = 1.8 V
POFFSET Supply power dissipation: VOFFSET(5) VOFFSET = 8.75 V 141 mW
VOFFSET = 8.5 V
PBIAS Supply power dissipation: VBIAS(5) VBIAS = 16.5 V 22 mW
VBIAS = 16 V
PRESET Supply power dissipation: VRESET VRESET = –10.5 V 108 mW
VRESET = –10 V
PTOTAL Supply power dissipation: Total 1110 mW
LPSDR INPUT(6)
VIH(DC) DC input high voltage(7) 0.7 × VDD VDD + 0.3 V
VIL(DC) DC input low voltage(7) –0.3 0.3 × VDD V
VIH(AC) AC input high voltage(7) 0.8 × VDD VDD + 0.3 V
VIL(AC) AC input low voltage –0.3 0.2 × VDD V
∆VT Hysteresis (VT+ – VT–) Figure 9 0.1 × VDD 0.4 × VDD V
IIL Low–level input current VDD = 1.95 V; VI = 0 V –100 nA
IIH High–level input current VDD = 1.95 V; VI = 1.95 V 300 nA
LPSDR OUTPUT(8)
VOH DC output high voltage IOH = –2 mA 0.8 × VDD V
VOL DC output low voltage IOL = 2 mA 0.2 × VDD V
CAPACITANCE
CIN Input capacitance LPSDR ƒ = 1 MHz 10 pF
Input capacitance SubLVDS ƒ = 1 MHz 20
COUT Output capacitance ƒ = 1 MHz 10 pF
CRESET Reset group capacitance ƒ = 1 MHz; (1152 × 144) micromirrors 350 400 450 pF
CTEMP Temperature sense diode capacitance ƒ = 1 MHz 20 pF
(1) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
(2) All voltage values are with respect to the ground pins (VSS).
(3) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than the specified limit.
(4) Supply power dissipation based on non–compressed commands and data.
(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit.
(6) LPSDR input specifications are for pin DMD_DEN_ARSTZ.
(7) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.
(8) LPSDR output specification is for pins LS_RDATA_A and LS_RDATA_B.
(9) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are also required.
(10) Typical current consumption is application and video content dependent. Please see a TI applications engineer for additional information.