DLPS210 March   2021 DLP651NE

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5.    
    6. 6.5  Thermal Information
    7. 6.6  Electrical Characteristics
    8. 6.7  Switching Characteristics
    9.    
    10. 6.8  Timing Requirements
    11.    
    12. 6.9  System Mounting Interface Loads
    13.    
    14. 6.10 Micromirror Array Physical Characteristics
    15.    
    16. 6.11 Micromirror Array Optical Characteristics
    17.    
    18. 6.12 Window Characteristics
    19. 6.13 Chipset Component Usage Specification
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Temperature Sensor Diode
  9. Power Supply Recommendations
    1. 9.1 Power Supply Sequence Requirements
    2. 9.2 DMD Power Supply Power-Up Procedure
    3. 9.3 DMD Power Supply Power-Down Procedure
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Impedance Requirements
    3. 10.3 Layers
    4. 10.4 Trace Width, Spacing
    5. 10.5 Power
    6. 10.6 Trace Length Matching Recommendations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
  • FYP|149
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and Functions

GUID-85C79EEC-6D3E-4D5D-AD07-F00B74EAC9EB-low.gifFigure 5-1 FYP Package149-Pin CPGABottom View
Table 5-1 Package Pinout
Pin Input-output (1) Pin Description Trace Length (mm)
Name Pad ID
D_AP(0) J1 I High–speed Differential Data Pair lane A0 18.09088
D_AN(0) H1 I High–speed Differential Data Pair lane A0 18.0916
D_AP(1) G1 I High–speed Differential Data Pair lane A1 18.11696
D_AN(1) F1 I High–speed Differential Data Pair lane A1 18.11641
D_AP(2) A3 I High–speed Differential Data Pair lane A2 11.11822
D_AN(2) A4 I High–speed Differential Data Pair lane A2 11.11745
D_AP(3) D2 I High–speed Differential Data Pair lane A3 12.04461
D_AN(3) C2 I High–speed Differential Data Pair lane A3 12.04491
D_AP(4) F2 I High–speed Differential Data Pair lane A4 15.1345
D_AN(4) E2 I High–speed Differential Data Pair lane A4 15.13457
D_AP(5) A5 I High–speed Differential Data Pair lane A5 12.80888
D_AN(5) A6 I High–speed Differential Data Pair lane A5 12.80825
D_AP(6) A7 I High–speed Differential Data Pair lane A6 6.34763
D_AN(6) A8 I High–speed Differential Data Pair lane A6 6.34706
D_AP(7) A9 I High–speed Differential Data Pair lane A7 4.45653
D_AN(7) A10 I High–speed Differential Data Pair lane A7 4.45875
DCLK_AP C1 I High–speed Differential Clock A 15.08029
DCLK_AN D1 I High–speed Differential Clock A 15.07977
D_BP(0) A11 I High–speed Differential Data Pair lane B0 4.06642
D_BN(0) A12 I High–speed Differential Data Pair lane B0 4.06697
D_BP(1) A13 I High–speed Differential Data Pair lane B1 6.42676
D_BN(1) A14 I High–speed Differential Data Pair lane B1 6.42716
D_BP(2) A15 I High–speed Differential Data Pair lane B2 11.90485
D_BN(2) A16 I High–speed Differential Data Pair lane B2 11.90509
D_BP(3) A18 I High–speed Differential Data Pair lane B3 13.80223
D_BN(3) A19 I High–speed Differential Data Pair lane B3 13.80269
D_BP(4) D19 I High–speed Differential Data Pair lane B4 12.45294
D_BN(4) C19 I High–speed Differential Data Pair lane B4 12.45252
D_BP(5) H20 I High–speed Differential Data Pair lane B5 15.7909
D_BN(5) J20 I High–speed Differential Data Pair lane B5 15.79026
D_BP(6) D20 I High–speed Differential Data Pair lane B6 11.02899
D_BN(6) E20 I High–speed Differential Data Pair lane B6 11.02947
D_BP(7) F20 I High–speed Differential Data Pair lane B7 14.7517
D_BN(7) G20 I High–speed Differential Data Pair lane B7 14.75085
DCLK_BP B17 I High–speed Differential Clock B 9.17864
DCLK_BN B18 I High–speed Differential Clock B 9.17821
LS_WDATA_P T10 I LVDS Data 11.27905
LS_WDATA_N R11 I LVDS Data 6.76474
LS_CLK_P R9 I LVDS CLK 13.5461
LS_CLK_N R10 I LVDS CLK 12.56934
LS_RDATA_A_BISTA T13 O LVCMOS Output 3.12045
BIST_B T12 O LVCMOS Output 5.63628
AMUX_OUT B20 O Analog Test Mux 9.3849
DMUX_OUT R14 O Digital Test Mux 3.85333
DMD_DEN_ARSTZ T11 I ARSTZ 5.86593
TEMP_N R8 I Temp Diode N 14.63792
TEMP_P R7 I Temp Diode P 15.93219
VDD B7, B13, C18, E3, H3, J2, K3, L2, L19, M1, M2, N3, N19, P2, P18, R3, R5, R12, R17, R19, T2, T4, T6, T8, T18 P Digital Core Supply Voltage Plane
VDDA B4, B9, B11, B16, C20, D3, E18, G2, G19 P HSSI Supply Voltage Plane
VRESET B3, R1 P Supply Voltage for Negative Bias of Micromirror reset signal Plane
VBIAS E1, P1 P Supply Voltage for Positive Bias of Micromirror reset signal Plane
VOFFSET A20, B2, T1, T20 P Supply voltage for HVCMOS logic,stepped up logic level Plane
VSS A17, B6, B10, B14, D18, F3, F19, J3, K2, K19, L1, L3, M3, N2, N18, N20, P3, P20, R2, R4, R6, R13, R20, T5, T7, T16, T17, T19 G Ground Plane
VSSA B5, B8, B12, B15, B19, C3, E19, G3, H2, H19, K1, N1, P19, R18, T3, T9 G Ground Plane
N/C R15,T14,T15,R16,H18,J18,G18,J19,F18,K20,K18,M19,L20,M18,L18,M20 No Connect
I=Input, O=Output, P=Power, G=Ground, NC = No Connect