DLPS210 March   2021 DLP651NE

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5.    
    6. 6.5  Thermal Information
    7. 6.6  Electrical Characteristics
    8. 6.7  Switching Characteristics
    9.    
    10. 6.8  Timing Requirements
    11.    
    12. 6.9  System Mounting Interface Loads
    13.    
    14. 6.10 Micromirror Array Physical Characteristics
    15.    
    16. 6.11 Micromirror Array Optical Characteristics
    17.    
    18. 6.12 Window Characteristics
    19. 6.13 Chipset Component Usage Specification
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Temperature Sensor Diode
  9. Power Supply Recommendations
    1. 9.1 Power Supply Sequence Requirements
    2. 9.2 DMD Power Supply Power-Up Procedure
    3. 9.3 DMD Power Supply Power-Down Procedure
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Impedance Requirements
    3. 10.3 Layers
    4. 10.4 Trace Width, Spacing
    5. 10.5 Power
    6. 10.6 Trace Length Matching Recommendations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
  • FYP|149
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Recommended Operating Conditions

Over operating free-air temperature range and supply voltages (unless otherwise noted) (1)
Parameter Name MIN NOM MAX UNIT
Supply Voltages (2) (3)
VDD Supply voltage for LVCMOS core logic and low speed interface (LSIF) 1.71 1.8 1.95 V
VDDA Supply voltage for high speed serial interface (HSSI) receivers 1.71 1.8 1.95 V
VOFFSET Supply voltage for HVCMOS and micromirror electrode (4) 9.5 10 10.5 V
VBIAS Supply voltage for micromirror electrode 15.5 16 16.5 V
VRESET Supply voltage for micromirror electrode –12.5 –12 –11.5 V
| VDDA – VDD | Supply voltage delta, absolute value (5) 0.3 V
| VBIASVOFFSET | Supply voltage delta, absolute value (6) 10.5 V
| VBIAS – VRESET | Supply voltage delta, absolute value 29 V
LVCMOS Input
VIH High level input voltage (7) 0.7 x VDD V
VIL Low level input voltage (7) 0.3 x VDD V
Low Speed Interface (LSIF)
fCLOCK LSIF clock frequency (LS_CLK) (8) 108 120 130 MHz
DCDIN LSIF duty cycle distortion (LS_CLK) 44 56 %
| VID | LSIF differential input voltage magnitude (8) 150 350 440 mV
VLVDS LSIF voltage. (8) 575 1520 mV
VCM Common mode voltage. (8) 700 900 1300 mV
ZLINE Line differential impedance (PWB/trace) 90 100 110 Ω
ZIN Internal differential termination resistance 80 100 120 Ω
High Speed Serial Interface (HSSI)
fCLOCK HSSI clock frequency (DCLK) (9) 1.2 1.6 GHz
DCDIN HSSI duty cycle distortion (DCLK) 44 50 56 %
| VID | Data HSSI differential input voltage magnitude Data Lane (9) 100 600 mV
| VID | CLK HSSI differential input voltage magnitude Clock Lane (9) 295 600 mV
VCMDC Data Input common mode voltage (DC) Data Lane (9) 200 600 800 mV
VCMDC CLK Input common mode voltage (DC) Clk Lane (9) 200 600 800 mV
VCMACp-p AC peak to peak (ripple) on common mode voltage of Data Lane and Clock Lane (9)     100 mV
ZLINE Line differential impedance (PWB/trace) 100 Ω
ZIN Internal differential termination resistance. ( RXterm ) 80 100 120 Ω
Environmental
TARRAY Array temperature, long-term operational. (10) (11) (12) (13) 10 40 to 70 °C
Array temperature, short-term operational, 500 hr max. (11) (14) 0 10 °C
TDP-AVG Average dew point temperature (non-condensing)(15) 28 °C
TDP-ELR Elevated dew point temperature range (non-condensing)(16) 28 36 °C
CTELR Cumulative time in elevated dew point temperature range 24 Months
QAP-ILL Window aperture illumination overfill(17) (18) 17 W/cm2
LAMP ILLUMINATION
ILLUV Illumination wavelength < 395 nm (10) 0.68 2 mW/cm2
ILLVIS Illumination wavelengths between 395 nm and 800 nm 29.3 W/cm2
ILLIR Illumination wavelength > 800 nm 10 mW/cm2
SOLID STATE ILLUMINATION
ILLUV Illumination wavelength < 410 nm (10) 3 mW/cm2
ILLVIS Illumination wavelengths between 410 nm and 800 nm 34.7 W/cm2
ILLIR Illumination wavelength > 800 nm 10 mW/cm2
Per Figure 6-1, the maximum operational array temperature should be de-rated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Micromirror Landed Duty Cycle for a definition of micromirror landed duty cycle.
The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CTELR.
The active area of the DMD is surrounded by an aperture on the inside of the DMD window surface that masks structures of the DMD device assembly from normal view.  The aperture is sized to anticipate several optical conditions. Overfill light illuminating the area outside the active array can scatter and create adverse effects to the performance of an end application using the DMD. The illumination optical system should be designed to minimize light flux incident outside the active array. Depending on the particular system's optical architecture and assembly tolerances, the amount of overfill light on the outside of the active array may cause system performance degradation.
Applies to the region in red in Figure 6-2.