DLPS210 March   2021 DLP651NE

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5.    
    6. 6.5  Thermal Information
    7. 6.6  Electrical Characteristics
    8. 6.7  Switching Characteristics
    9.    
    10. 6.8  Timing Requirements
    11.    
    12. 6.9  System Mounting Interface Loads
    13.    
    14. 6.10 Micromirror Array Physical Characteristics
    15.    
    16. 6.11 Micromirror Array Optical Characteristics
    17.    
    18. 6.12 Window Characteristics
    19. 6.13 Chipset Component Usage Specification
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Temperature Sensor Diode
  9. Power Supply Recommendations
    1. 9.1 Power Supply Sequence Requirements
    2. 9.2 DMD Power Supply Power-Up Procedure
    3. 9.3 DMD Power Supply Power-Down Procedure
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Impedance Requirements
    3. 10.3 Layers
    4. 10.4 Trace Width, Spacing
    5. 10.5 Power
    6. 10.6 Trace Length Matching Recommendations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
  • FYP|149
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

Over operating free-air temperature range and supply voltages (unless otherwise noted)
SYMBOL PARAMETER (1) (2) TEST CONDITIONS (1) MIN TYP MAX UNIT
Current – Typical
IDD Supply current VDD (3) 800 1250 mA
IDDA Supply current VDDA (3) 900 1200 mA
IDDA Supply current VDDA (3) single macro mode 500 600 mA
IOFFSET Supply current VOFFSET (4) (5) 23 35 mA
IBIAS Supply current VBIAS (4) (5) 2.4 3.8 mA
IRESET Supply current VRESET (5) -10.5 -7.7 mA
Power – Typical
PDD Supply power dissipation VDD (3) 1440 2437.5 mW
PDDA Supply power dissipation VDDA (3) 1620 2340 mW
PDDA Supply power dissipation VDDA (3) single macro mode 900 1170 mW
POFFSET Supply power dissipation VOFFSET (4) (5) 230 367.5 mW
PBIAS Supply power dissipation VBIAS (4) (5) 38.4 62.7 mW
PRESET Supply power dissipation VRESET (5) 92.4 131.25 mW
PTOTAL Supply power dissipation Total 3420.8 5338.95 mW
LVCMOS Input
IIL Low level input current (6) VDD = 1.95 V , VI = 0 V –100 nA
IIH High level input current (6) VDD = 1.95 V , VI = 1.95 V 135 uA
LVCMOS Output
VOH DC output high voltage (7) IOH = -2 mA 0.8 x VDD V
VOL DC output low voltage (7) IOL = 2 mA 0.2 x VDD V
Receiver Eye Characteristics
A1 Minimum data eye opening (8) 100 600 mV
A1 Minimum clock eye opening (8) 295 600 mV
A2 Maximum signal swing (8) (9) 600 mV
X1 Maximum eye closure (8) 0.275 UI
X2 Maximum eye closure (8) 0.4 UI
| tDRIFT | Drift between Clock and Data between Training Patterns 20 ps
Capacitance
CIN Input capacitance LVCMOS f = 1 MHz 10 pF
CIN Input capacitance LSIF (low speed interface) f = 1 MHz 20 pF
CIN Input capacitance HSSI (high speed serial interface) - Differential - Clock and Data pins f = 1 MHz 5 pF
COUT Output capacitance f = 1 MHz 10 pF
All power supply connections are required to operate the DMD: VDD, VDDA, VOFFSET, VBIAS, and VRESET. All VSS connections are required to operate the DMD.
All voltage values are with respect to the ground pins (VSS).
To prevent excess current, the supply voltage delta | VDDA – VDD | must be less than specified limit.
To prevent excess current, the supply voltage delta | VBIAS – VOFFSET | must be less than specified limit.
Supply power dissipation based on 3 global resets in 200 µs.
LVCMOS input specifications are for pin DMD_DEN_ARSTZ.
LVCMOS output specification is for pins LS_RDATA_A and LS_RDATA_B.
Refer to Figure 6-12 (1e-12 BER).