DLPS210 March   2021 DLP651NE

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5.    
    6. 6.5  Thermal Information
    7. 6.6  Electrical Characteristics
    8. 6.7  Switching Characteristics
    9.    
    10. 6.8  Timing Requirements
    11.    
    12. 6.9  System Mounting Interface Loads
    13.    
    14. 6.10 Micromirror Array Physical Characteristics
    15.    
    16. 6.11 Micromirror Array Optical Characteristics
    17.    
    18. 6.12 Window Characteristics
    19. 6.13 Chipset Component Usage Specification
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Temperature Sensor Diode
  9. Power Supply Recommendations
    1. 9.1 Power Supply Sequence Requirements
    2. 9.2 DMD Power Supply Power-Up Procedure
    3. 9.3 DMD Power Supply Power-Down Procedure
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Impedance Requirements
    3. 10.3 Layers
    4. 10.4 Trace Width, Spacing
    5. 10.5 Power
    6. 10.6 Trace Length Matching Recommendations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
  • FYP|149
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Timing Requirements

Over operating free-air temperature range and supply voltages (unless otherwise noted)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LVCMOS
tr Rise time (1) 20% to 80% reference points 25 ns
tf Fall time (1) 80% to 20% reference points 25 ns
Low Speed Interface (LSIF)
tr Rise time (2) 20% to 80% reference points 450 ps
tf Fall time (2) 80% to 20% reference points 450 ps
tW(H) Pulse duration high (3) LS_CLK. 50% to 50% reference points 3.1 ns
tW(L) Pulse duration low (3) LS_CLK. 50% to 50% reference points 3.1 ns
tsu Setup time (4) LS_WDATA valid before rising edge of LS_CLK (differential) 1.5 ns
th Hold time (4) LS_WDATA valid after rising edge of LS_CLK (differential) 1.5 ns
High Speed Serial Interface (HSSI)
tr Rise time(5) - Data from -A1 to A1 minimum eye height specification 50 115 ps
tr Rise time(5) - Clock from -A1 to A1 minimum eye height specification 50 135 ps
tf Fall time(5) - Data from A1 to -A1 minimum eye height specification 50 115 ps
tf Fall time(5) - Clock from A1 to -A1 minimum eye height specification 50 135 ps
tW(H) Pulse duration high (6) DCLK. 50% to 50% reference points 0.275 ns
tW(L) Pulse duration low (6) DCLK. 50% to 50% reference points 0.275 ns
tc Cycle time (6) DCLK 0.625 0.833 ns
See Figure 6-9 and Figure 6-10 LVCMOS Rise, Fall Time SLew Rate Figures. Specification is for DMD_DEN_ARSTZ pin (LVCMOS).
See Figure 6-6 for rise and fall time for LSIF.
See Figure 6-5 for pulse duration high and low time for LSIF.
See Figure 6-5 for setup and hold time for LSIF.
See Figure 6-11 for rise and fall time for HSSI.
See Figure 6-13 for pulse duration high and low and cycle time for HSSI.