DLPS061D May 2015 – May 2017 DLP7000UV
Reliable function and operation of the DLP7000UV requires that it be used in conjunction with the other components of the chipset. A dedicated chipset provides developers easier access to the DMD as well as high speed, independent micromirror control.
Electrically, the DLP7000UV consists of a two-dimensional array of 1-bit CMOS memory cells, organized in a grid of 1024 memory cell columns by 768 memory cell rows. The CMOS memory array is addressed on a row-by-row basis, over two 16-bit low voltage differential signaling (LVDS) double data rate (DDR) buses. Addressing is handled via a serial control bus. The specific CMOS memory access protocol is handled by the DLPC410 digital controller.