DLPS061D May   2015  – May 2017 DLP7000UV


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Storage Conditions
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  LVDS Timing Requirements
    8. 7.8  LVDS Waveform Requirements
    9. 7.9  Serial Control Bus Timing Requirements
    10. 7.10 Systems Mounting Interface Loads
    11. 7.11 Micromirror Array Physical Characteristics
    12. 7.12 Micromirror Array Optical Characteristics
    13. 7.13 Window Characteristics
    14. 7.14 Chipset Component Usage Specification
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DLPC410 - Digital Controller for DLP Discovery 4100 Chipset
      2. 8.3.2 DLPA200 DMD Micromirror Driver
      3. 8.3.3 DLPR410 - PROM for DLP Discovery 4100 Chipset
      4. 8.3.4 DLP7000 - DLP 0.7 XGA 2xLVDS UV Type-A DMD
        1. DLP7000UV Chipset Interfaces
          1. DLPC410 Interface Description
            1. DLPC410 IO
            2. Initialization
            3. DMD Device Detection
            4. Power Down
        2. DLPC410 to DMD Interface
          1. DLPC410 to DMD IO Description
          2. Data Flow
        3. DLPC410 to DLPA200 Interface
          1. DLPA200 Operation
          2. DLPC410 to DLPA200 IO Description
        4. DLPA200 to DLP7000UV Interface Overview
      5. 8.3.5 Measurement Conditions
    4. 8.4 Device Functional Modes
      1. 8.4.1 DMD Operation
        1. Single Block Mode
        2. Dual Block Mode
        3. Quad Block Mode
        4. Global Mode
    5. 8.5 Window Characteristics and Optics
      1. 8.5.1 Optical Interface and System Image Quality
      2. 8.5.2 Numerical Aperture and Stray Light Control
      3. 8.5.3 Pupil Match
      4. 8.5.4 Illumination Overfill
    6. 8.6 Micromirror Array Temperature Calculation
      1. 8.6.1 Package Thermal Resistance
      2. 8.6.2 Case Temperature
      3. 8.6.3 Micromirror Array Temperature Calculation
    7. 8.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 8.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 8.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 8.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 8.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 DMD Reflectivity Characteristics
      2. 9.1.2 Design Considerations Influencing DMD Reflectivity
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Power-Up Sequence (Handled by the DLPC410)
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Impedance Requirements
      2. 11.1.2 PCB Signal Routing
      3. 11.1.3 Fiducials
      4. 11.1.4 PCB Layout Guidelines
        1. DMD Interface
          1. Trace Length Matching
        2. DLP7000UV Decoupling
          1. Decoupling Capacitors
        3. VCC and VCC2
        4. DMD Layout
        5. DLPA200
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
        1. Device Marking
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


Layout Guidelines

The DLP7000UV is part of a chipset that is controlled by the DLPC410 in conjunction with the DLPA200. These guidelines are targeted at designing a PCB board with these components.

Impedance Requirements

Signals should be routed to have a matched impedance of 50 Ω ±10% except for LVDS differential pairs (DMD_DAT_Xnn, DMD_DCKL_Xn, and DMD_SCTRL_Xn), which should be matched to 100 Ω ±10% across each pair.

PCB Signal Routing

When designing a PCB board for the DLP7000UV controlled by the DLPC410 in conjunction with the DLPA200, the following are recommended:

Signal trace corners should be no sharper than 45°. Adjacent signal layers should have the predominate traces routed orthogonal to each other. TI recommends that critical signals be hand routed in the following order: DDR2 Memory, DMD (LVDS signals), then DLPA200 signals.

TI does not recommend signal routing on power or ground planes.

TI does not recommend ground plane slots.

High speed signal traces should not crossover slots in adjacent power and/or ground planes.

Table 7. Important Signal Trace Constraints

DMD_DCKL_xn, and DMD_SCTRL_xn)
P-to-N data, clock, and SCTRL: <10 mils (0.25 mm); Pair-to-pair <10 mils (0.25 mm); Bundle-to-bundle <2000 mils (50 mm, for example DMD_DAT_Ann to DMD_DAT_Bnn)
Trace width: 4 mil (0.1 mm)
Trace spacing: In ball field – 4 mil (0.11 mm); PCB etch – 14 mil (0.36 mm)
Maximum recommended trace length <6 inches (150 mm)

Table 8. Power Trace Widths and Spacing

GND Maximize 5 mil (0.13 mm) Maximize trace width to connecting pin as a minimum
VCC, VCC2 20 mil (0.51 mm) 10 mil (0.25 mm)
MBRST[15:0] 10 mil (0.25 mm) 10 mil (0.25 mm)


Fiducials for automatic component insertion should be 0.05-inch copper with a 0.1-inch cutout (antipad). Fiducials for optical auto insertion are placed on three corners of both sides of the PCB.

PCB Layout Guidelines

A target impedance of 50 Ω for single ended signals and 100 Ω between LVDS signals is specified for all signal layers.

DMD Interface

The digital interface from the DLPC410 to the DMD are LVDS signals that run at clock rates up to 400 MHz. Data is clocked into the DMD on both the rising and falling edge of the clock, so the data rate is 800 MHz. The LVDS signals should have 100-Ω differential impedance. The differential signals should be matched but kept as short as possible. Parallel termination at the LVDS receiver is in the DMD; therefore, on board termination is not necessary.

Trace Length Matching

The DLPC410 DMD data signals require precise length matching. Differential signals should have impedance of 100 Ω (with 5% tolerance). It is important that the propagation delays are matched. The maximum differential pair uncoupled length is 100 mils with a relative propagation delay of ±25 mil between the p and n. Matching all signals exactly will maximize the channel margin. The signal path through all boards, flex cables and internal DMD routing must be considered in this calculation.

DLP7000UV Decoupling

General decoupling capacitors for the DLP7000UV should be distributed around the PCB and placed to minimize the distance from IC voltage and ground pads. Each decoupling capacitor (0.1 µF recommended) should have vias directly to the ground and power planes. Via sharing between components (discreet or integrated) is discouraged. The power and ground pads of the DLP7000UV should be tied to the voltage and ground planes with their own vias.

Decoupling Capacitors

Decoupling capacitors should be placed to minimize the distance from the decoupling capacitor to the supply and ground pin of the component. It is recommended that the placement of and routing for the decoupling capacitors meet the following guidelines:

  • The supply voltage pin of the capacitor should be located close to the device supply voltage pin(s). The decoupling capacitor should have vias to ground and voltage planes. The device can be connected directly to the decoupling capacitor (no via) if the trace length is less than 0.1 inch. Otherwise, the component should be tied to the voltage or ground plane through separate vias.
  • The trace lengths of the voltage and ground connections for decoupling capacitors and components should be less than 0.1 inch to minimize inductance.
  • The trace width of the power and ground connection to decoupling capacitors and components should be as wide as possible to minimize inductance.
  • Connecting decoupling capacitors to ground and power planes through multiple vias can reduce inductance and improve noise performance.
  • Decoupling performance can be improved by utilizing low ESR and low ESL capacitors.

VCC and VCC2

The VCC pins of the DMD should be connected directly to the DMD VCC plane. Decoupling for the VCC should be distributed around the DMD and placed to minimize the distance from the voltage and ground pads. Each decoupling capacitor should have vias directly connected to the ground and power planes. The VCC and GND pads of the DMD should be tied to the VCC and ground planes with their own vias.

The VCC2 voltage can be routed to the DMD as a trace. Decoupling capacitors should be placed to minimize the distance from the VCC2 and ground pads of the DMD. Using wide etch from the decoupling capacitors to the DMD connection will reduce inductance and improve decoupling performance.

DMD Layout

See the respective sections in this data sheet for package dimensions, timing and pin out information.


The DLPA200 generates the micromirror clocking pulses for the DMD. The DMD-drive outputs from the DLPA200 (MBRST[15:0]) should be routed with minimum trace width of 11 mil and a minimum spacing of 15 mil. The VCC and VCC2 traces from the output capacitors to the DLPA200 should also be routed with a minimum trace width and spacing of 11 mil and 15 mil, respectively. See the DLPA200 customer data sheet (DLPS015) for mechanical package and layout information.

Layout Example

For LVDS (and other differential signal) pairs and groups, it is important to match trace lengths. In the area of the dashed lines, Figure 21 shows correct matching of signal pair lengths with serpentine sections to maintain the correct impedance.

DLP7000UV LVDS-trace_length_matching.png Figure 21. Mitering LVDS Traces to Match Lengths