DLPS061D May   2015  – May 2017 DLP7000UV

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Storage Conditions
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  LVDS Timing Requirements
    8. 7.8  LVDS Waveform Requirements
    9. 7.9  Serial Control Bus Timing Requirements
    10. 7.10 Systems Mounting Interface Loads
    11. 7.11 Micromirror Array Physical Characteristics
    12. 7.12 Micromirror Array Optical Characteristics
    13. 7.13 Window Characteristics
    14. 7.14 Chipset Component Usage Specification
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DLPC410 - Digital Controller for DLP Discovery 4100 Chipset
      2. 8.3.2 DLPA200 DMD Micromirror Driver
      3. 8.3.3 DLPR410 - PROM for DLP Discovery 4100 Chipset
      4. 8.3.4 DLP7000 - DLP 0.7 XGA 2xLVDS UV Type-A DMD
        1. 8.3.4.1 DLP7000UV Chipset Interfaces
          1. 8.3.4.1.1 DLPC410 Interface Description
            1. 8.3.4.1.1.1 DLPC410 IO
            2. 8.3.4.1.1.2 Initialization
            3. 8.3.4.1.1.3 DMD Device Detection
            4. 8.3.4.1.1.4 Power Down
        2. 8.3.4.2 DLPC410 to DMD Interface
          1. 8.3.4.2.1 DLPC410 to DMD IO Description
          2. 8.3.4.2.2 Data Flow
        3. 8.3.4.3 DLPC410 to DLPA200 Interface
          1. 8.3.4.3.1 DLPA200 Operation
          2. 8.3.4.3.2 DLPC410 to DLPA200 IO Description
        4. 8.3.4.4 DLPA200 to DLP7000UV Interface Overview
      5. 8.3.5 Measurement Conditions
    4. 8.4 Device Functional Modes
      1. 8.4.1 DMD Operation
        1. 8.4.1.1 Single Block Mode
        2. 8.4.1.2 Dual Block Mode
        3. 8.4.1.3 Quad Block Mode
        4. 8.4.1.4 Global Mode
    5. 8.5 Window Characteristics and Optics
      1. 8.5.1 Optical Interface and System Image Quality
      2. 8.5.2 Numerical Aperture and Stray Light Control
      3. 8.5.3 Pupil Match
      4. 8.5.4 Illumination Overfill
    6. 8.6 Micromirror Array Temperature Calculation
      1. 8.6.1 Package Thermal Resistance
      2. 8.6.2 Case Temperature
      3. 8.6.3 Micromirror Array Temperature Calculation
    7. 8.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 8.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 8.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 8.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 8.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 DMD Reflectivity Characteristics
      2. 9.1.2 Design Considerations Influencing DMD Reflectivity
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Power-Up Sequence (Handled by the DLPC410)
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Impedance Requirements
      2. 11.1.2 PCB Signal Routing
      3. 11.1.3 Fiducials
      4. 11.1.4 PCB Layout Guidelines
        1. 11.1.4.1 DMD Interface
          1. 11.1.4.1.1 Trace Length Matching
        2. 11.1.4.2 DLP7000UV Decoupling
          1. 11.1.4.2.1 Decoupling Capacitors
        3. 11.1.4.3 VCC and VCC2
        4. 11.1.4.4 DMD Layout
        5. 11.1.4.5 DLPA200
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
        1. 12.1.1.1 Device Marking
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Specifications

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
ELECTRICAL
VCC Voltage applied to VCC (2) (3) –0.5 4 V
VCCI Voltage applied to VCCI (2) (3) –0.5 4 V
VCC2 Voltage applied to VVCC2 (2) (3) (4) –0.5 8 V
VMBRST Micromirror clocking pulse waveform voltage applied to MBRST[15:0] Input Pins (supplied by DLPA200) –28 28 V
|VCC – VCCI| Supply voltage delta (absolute value) (4) 0.3 V
Voltage applied to all other input pins (2) –0.5 VCC + 0.3 V
|VID| Maximum differential voltage, damage can occur to internal termination resistor if exceeded, see Figure 2 700 mV
IOH Current required from a high-level output VOH = 2.4 V –20 mA
IOL Current required from a low-level output VOL = 0.4 V 15 mA
ENVIRONMENTAL
TC Case temperature – operational (5) 20 30 °C
Case temperature – non-operational (5) –40 80 °C
TGRADIENT Device temperature gradient – operational (6) 10 °C
RH Relative humidity (non-condensing) 95 %RH
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS (ground).
Voltages VCC, VCCI, and VCC2 are required for proper DMD operation.
Exceeding the recommended allowable absolute voltage difference between VCC and VCCI may result in excess current draw. The difference between VCC and VCCI, |VCC – VCCI|, should be less than the specified limit.
DMD Temperature is the worst-case of any test point shown in Case Temperature, or the active array as calculated by the Micromirror Array Temperature Calculation.
As either measured, predicted, or both between any two points -- measured on the exterior of the package, or as predicted at any point inside the micromirror array cavity. Refer to Case Temperature and Micromirror Array Temperature Calculation.

Storage Conditions

are applicable before the DMD is installed in the final product.
MIN MAX UNIT
TDMD Storage temperature –40 80 °C
RH Relative humidity (non-condensing) 95 %RH

ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) All pins except MBRST[0:15] ±2000 V
MBRST[0:15] pins <250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible if necessary precautions are taken.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
MIN NOM MAX UNIT
ELECTRICAL
VCC Supply voltage for LVCMOS core logic (2) (3) 3.0 3.3 3.6 V
VCCI Supply voltage for LVDS receivers (2) (3) 3.0 3.3 3.6 V
VCC2 Mirror electrode and HVCMOS supply voltage (2) (3) 7.25 7.5 7.75 V
VMBRST Clocking pulse waveform voltage applied to MBRST[15:0] input pins (supplied by DLPA200) –27 26.5 V
|VCC – VCCI| Supply voltage delta (absolute value) (3) 0.3 V
ENVIRONMENTAL
Illumination power density (4) (5) < 363 nm (6) 2 mW/cm2
363 to 400 nm (7) 2.5 W/cm2
3.7 W
400 to 420 nm (7) 11 W/cm2
16.2 W
363 to 420 nm total (7)(8) 11 W/cm2
16.2 W
> 420 nm Thermally limited (7) W/cm2
TC Case/array temperature (9) (10) 20 30 (11) °C
TGRADIENT Device temperature gradient – operational (12) 10 °C
RH Relative humidity (non-condensing) 95 %RH
Operating landed duty cycle (13) 25%
The functional performance of the device specified in this datasheet is achieved when operating the device within the limits defined by the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the Recommended Operating Conditions limits.
All voltages referenced to VSS (ground).
Voltages VCC, VCCI, and VCC2, are required for proper DMD operation.
Various application parameters can affect optimal, long-term performance of the DMD, including illumination spectrum, illumination power density, micromirror landed duty cycle, ambient temperature (both storage and operating), case temperature, and power-on or power-off duty cycle. TI recommends that application-specific effects be considered as early as possible in the design cycle.
Total integrated illumination power density, above or below the indicated wavelength threshold or in the indicated wavelength range.
The maximum operating conditions for operating temperature and illumination power density for wavelengths < 363 nm should not be implemented simultaneously.
Also limited by the resulting micromirror array temperature. Refer to Case Temperature and Micromirror Array Temperature Calculation for information related to calculating the micromirror array temperature.
The total integrated illumination power density from 363 to 420 nm shall not exceed 11 W/cm2 (or 16.2 W evenly distributed on the active array area). Therefore if 2.5 W/cm2 of illumination is used in the 363 to 400 nm range, then illumination in the 400 to 420 nm range must be limited to 8.5 W/cm2.
In some applications, the total DMD heat load can be dominated by the amount of incident light energy absorbed. Refer to Micromirror Array Temperature Calculation for further details.
Temperature is the highest measured value of any test point shown in Figure 17 or the active array as calculated by the Micromirror Array Temperature Calculation.
Refer to Micromirror Array Temperature Calculation for thermal test point locations, package thermal resistance, and device temperature calculation.
As either measured, predicted, or both between any two points -- measured on the exterior of the package, or as predicted at any point inside the micromirror array cavity. Refer to Case Temperature and Micromirror Array Temperature Calculation.
Landed duty cycle refers to the percentage of time an individual micromirror spends landed in one state (12° or –12°) versus the other state (–12° or 12°).

Thermal Information

THERMAL METRIC (1) (2) DLP7000UV UNIT
FLP (LCCC)
203 PINS
Active micromirror array resistance to TP1 0.9 °C/W
The DMD is designed to conduct absorbed and dissipated heat to the back of the package where it can be removed by an appropriate heat sink. The heat sink and cooling system must be capable of maintaining the package within the temperature range specified in the Recommended Operating Conditions. The total heat load on the DMD is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

Electrical Characteristics

over the range of recommended supply voltage and recommended case operating temperature (unless otherwise noted)
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage (1),
See Figure 10
VCC = 3.0 V, IOH = –20 mA 2.4 V
VOL Low-level output voltage (1),
See Figure 10
VCC = 3.6 V, IOH = 15 mA 0.4 V
VMBRST Clocking Pulse Waveform applied to MBRST[29:0] Input Pins (supplied by DLPA200) -27 26.5 V
IOZ High impedance output current (1) VCC = 3.6 V 10 µA
IOH High-level output current (1) VOH = 2.4 V, VCC ≥ 3 V –20 mA
VOH = 1.7 V, VCC ≥ 2.25 V –15
IOL Low-level output current (1) VOL = 0.4 V, VCC ≥ 3 V 15 mA
VOL = 0.4 V, VCC ≥ 2.25 V 14
VIH High-level input voltage (1) 1.7 VCC + .3 V
VIL Low-level input voltage (1) –0.3 0.7 V
IIL Low-level input current (1) VCC = 3.6 V, VI = 0 V –60 µA
IIH High-level input current (1) VCC = 3.6 V, VI = VCC 200 µA
ICC Current into VCC pin VCC = 3.6 V 1475 mA
ICCI Current into VCCI pin (2) VCCI = 3.6 V 450 mA
ICC2 Current into VCC2 pin VCC2 = 8.75 V 25 mA
PD Power dissipation 2.0 W
ZIN Internal differential impedance 95 105 Ω
ZLINE Line differential impedance (PWB, Trace) 90 100 110 Ω
CI Input capacitance (1) f = 1 MHz 10 pF
CO Output capacitance (1) f = 1 MHz 10 pF
CIM Input capacitance for MBRST[0:15] pins f = 1 MHz 220 270 pF
Applies to LVCMOS pins only.
Exceeding the maximum allowable absolute voltage difference between VCC and VCCI may result in excess current draw. See the Absolute Maximum Ratings for details.

LVDS Timing Requirements

over operating free-air temperature range (unless otherwise noted); see Figure 1
MIN NOM MAX UNIT
fDCLK_* DCLK_* clock frequency \{where * = [A, or B]\} 200 400 MHz
tc Clock cycle - DLCK_* 2.5 ns
tw Pulse width - DLCK_* 1.25 ns
ts Setup time - D_*[15:0] and SCTRL_* before DCLK_* 0.35 ns
th Hold time, D_*[15:0] and SCTRL_* after DCLK_* 0.35 ns
tskew Skew between bus A and B –1.25 1.25 ns
DLP7000UV switch_char_lps026.gif Figure 1. LVDS Timing Waveforms

LVDS Waveform Requirements

over operating free-air temperature range (unless otherwise noted); see Figure 2
MIN NOM MAX UNIT
|VID| Input differential voltage (absolute difference) 100 400 600 mV
VCM Common mode voltage 1200 mV
VLVDS LVDS voltage 0 2000 mV
tr Rise time (20% to 80%) 100 400 ps
tr Fall time (80% to 20%) 100 400 ps
DLP7000UV lvdswavereqs_lps013.gif Figure 2. LVDS Waveform Requirements

Serial Control Bus Timing Requirements

over operating free-air temperature range (unless otherwise noted); see Figure 3 and Figure 4
MIN NOM MAX UNIT
fSCP_CLK SCP clock frequency 50 500 kHz
tSCP_SKEW Time between valid SCP_DI and rising edge of SCP_CLK –300 300 ns
tSCP_DELAY Time between valid SCP_DO and rising edge of SCP_CLK 960 ns
t SCP_EN Time between falling edge of SCP_EN and the first rising edge of SCP_CLK 30 ns
t_SCP Rise time for SCP signals 200 ns
tf_SCP Fall time for SCP signals 200 ns
DLP7000UV SCP_Timing_Parameters.gif Figure 3. Serial Communications Bus Timing Parameters
DLP7000UV inputrisefall_cmos_lps013.gif Figure 4. Serial Communications Bus Waveform Requirements

Systems Mounting Interface Loads

PARAMETER MIN NOM MAX UNIT
Maximum system mounting interface load to be applied to the: Thermal interface area (see Figure 5) 111 N
Electrical interface area 423 N
Datum A Interface area (see Figure 5 ) (1) 400 N
Combined loads of the thermal and electrical interface areas in excess of Datum A load shall be evenly distributed outside the Datum A area (423 + 111 – Datum A).
DLP7000UV System_interface_loadings_A.gif Figure 5. System Interface Loads

Micromirror Array Physical Characteristics

VALUE UNIT
M Number of active columns See Figure 6 1024 micromirrors
N Number of active rows 768 micromirrors
P Micromirror (pixel) pitch 13.68 µm
Micromirror active array width M × P 14.008 mm
Micromirror active array height N × P 10.506 mm
Micromirror active border Pond of micromirror (POM) (1) 6 micromirrors/side
The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM. These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical bias to tilt toward OFF.
DLP7000UV Micromirror_Array_Physical_DLPS061.gif
Refer to Micromirror Array Physical Characteristics for M, N, and P specifications.
Figure 6. Micromirror Array Physical Characteristics

Micromirror Array Optical Characteristics

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment optical performance involves making trade-offs between numerous component and system design parameters.

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
a Micromirror tilt angle DMD parked state (1) (2) (3), See Figure 12 0 degrees
DMD landed state (1) (4) (5)
See Figure 12
12
β Micromirror tilt angle tolerance (1) (4) (6) (7) (8) See Figure 12 –1 1 degrees
Micromirror crossover time (9) 4 22 µs
Micromirror switching time (10) 13 22 µs
Array switching time at 400 MHz with global reset (11) 43 µs
Non operating micromirrors (12) Non-adjacent micromirrors 10 micromirrors
Adjacent micromirrors 0
Orientation of the micromirror axis-of-rotation (13) See Figure 11 44 45 46 degrees
Micromirror array optical efficiency (14) (15) 363 to 420 nm, with all micromirrors in the ON state 66%
  1. Measured relative to the plane formed by the overall micromirror array.
  2. Parking the micromirror array returns all of the micromirrors to an essentially flat (0˚) state (as measured relative to the plane formed by the overall micromirror array).
  3. When the micromirror array is parked, the tilt angle of each individual micromirror is uncontrolled.
  4. Additional variation exists between the micromirror array and the package datums, as shown in the Mechanical, Packaging, and Orderable Information.
  5. When the micromirror array is landed, the tilt angle of each individual micromirror is dictated by the binary contents of the CMOS memory cell associated with each individual micromirror. A binary value of 1 will result in a micromirror landing in an nominal angular position of +12°. A binary value of 0 results in a micromirror landing in an nominal angular position of –12°.
  6. Represents the landed tilt angle variation relative to the Nominal landed tilt angle.
  7. Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different devices.
  8. For some applications, it is critical to account for the micromirror tilt angle variation in the overall System Optical Design. With some System Optical Designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field reflected from the micromirror array. With some System Optical Designs, the micromirror tilt angle variation between devices may result in colorimetry variations and/or system contrast variations.
  9. Micromirror crossover time is primarily a function of the natural response time of the micromirrors and is the time it takes for the micromirror to crossover to the other state, but does not include mechanical settling time.
  10. Micromirror switching time is the time before a micromirror may be addressed again. Crossover time plus mechanical settling time.
  11. Array switching is controlled and coordinated by the DLPC410 (DLPS024) and DLPA200 (DLPS015). Nominal Switching time depends on the system implementation and represents the time for the entire micromirror array to be refreshed (array loaded plus reset and mirror settling time).
  12. Non-operating micromirror is defined as a micromirror that is unable to transition nominally from the –12° position to +12° or vice versa.
  13. Measured relative to the package datums B and C, shown in the Mechanical, Packaging, and Orderable Information.
  14. The minimum or maximum DMD optical efficiency observed depends on numerous application-specific design variables, such as:
    • Illumination wavelength, bandwidth/line-width, degree of coherence
    • Illumination angle, plus angle tolerance
    • Illumination and projection aperture size, and location in the system optical path
    • IIlumination overfill of the DMD micromirror array
    • Aberrations present in the illumination source and/or path
    • Aberrations present in the projection path

    The specified nominal DMD optical efficiency is based on the following use conditions:
    • Visible illumination (363 to 420 nm)
    • Input illumination optical axis oriented at 24° relative to the window normal
    • Projection optical axis oriented at 0° relative to the window normal
    • f / 3.0 illumination aperture
    • f / 2.4 projection aperture

    Based on these use conditions, the nominal DMD optical efficiency results from the following four components:
    • Micromirror array fill factor: nominally 92%
    • Micromirror array diffraction efficiency: nominally 85%
    • Micromirror surface reflectivity: nominally 88%
    • Window transmission: nominally 98% for wavelengths 363 nm to 420 nm, applies to all angles 0° to 30° AOI (Angle of Incidence) (single pass, through two surface transitions)
  15. Does not account for the effect of micromirror switching duty cycle, which is application dependent. Micromirror switching duty cycle represents the percentage of time that the micromirror is actually reflecting light from the optical illumination path to the optical projection path. This duty cycle depends on the illumination aperture size, the projection aperture size, and the micromirror array update rate.

Window Characteristics

PARAMETER (1) CONDITIONS MIN TYP MAX UNIT
Window material designation Corning 7056
Window refractive index At wavelength 589 nm 1.487
Window flatness (2) Per 25 mm 4 fringes
Window artifact size Within the Window Aperture (3) 400 µm
Window aperture See (4)
Illumination overfill Refer to Illumination Overfill
Window transmittance, single–pass through both surfaces and glass (5) Within the wavelength range 363 nm to 420 nm. Applies to all angles 0 to 30 AOI 98%
See Window Characteristics and Optics for more information.
At a wavelength of 632.8 nm.
See the Mechanical, Packaging, and Orderable Information section at the end of this document for details regarding the size and location of the window aperture.
For details regarding the size and location of the window aperture, see the package mechanical characteristics listed in the Mechanical, Packaging, and Orderable Information section.
See the TI application report Wavelength Transmittance Considerations for DMD Window, DLPA031.

Chipset Component Usage Specification

The DLP7000UV is a component of one or more DLP chipsets. Reliable function and operation of the DLP7000UV requires that it be used in conjunction with the other components of the applicable DLP chipset, including those components that contain or implement TI DMD control technology. TI DMD control technology consists of the TI technology and devices for operating or controlling a DLP DMD.