DLPS015G april   2010  – june 2023 DLPA200

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Device Configurations Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics Control Logic
    6. 7.6  5-V Linear Regulator
    7. 7.7  Bias Voltage Boost Converter
    8. 7.8  Reset Voltage Buck-Boost Converter
    9. 7.9  VOFFSET/DMDVCC2 Regulator
    10. 7.10 Switching Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 5-V Linear Regulator
      2. 8.3.2 Bias Voltage Boost Converter
      3. 8.3.3 Reset Voltage Buck-Boost Converter
      4. 8.3.4 VOFFSET/DMDVCC2 Regulator
      5. 8.3.5 Serial Communications Port (SCP)
  10. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Component Selection Guidelines
  11. 10Power Supply Recommendations
    1. 10.1 Power Supply Rail Guidelines
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Grounding Guidelines
    2. 11.2 Thermal Considerations
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SERIAL COMMUNICATION PORT INTERFACE
A(1)Setup SCPEN low to SCPCKReference to rising edge of SCPCK360ns
B(1)Byte to byte delayNominally 1 SCPCK cycle, rising edge to rising edge1.9µs
C(1)Setup SCPDI to SCPEN highLast byte to secondary disable360ns
D(1)SCPCK frequency(2)0526kHz
SCPCK period1.92µs
E(1)SCPCK high or low time300ns
F(1)SCPDI set-up timeReference to falling edge of SCPCK300ns
G(1)SCPDI hold timeReference from falling edge of SCPCK300ns
H(1)SCPDO propagation delayReference from rising edge of SCPCK300ns
SCPEN, SCPCK, SCPDI, RESET filter (pulse reject)150ns
OUTPUT MICROMIRROR CLOCKING PULSES
FPREPPhased reset repetition frequency each output pin (non-overlapping)50kHz
FGREPGlobal reset repetition frequency all output pins50kHz
IRLKVRESET output leakage currentOE = 1, VRESET_RAIL = -28.5V-1-10µA
IBLKVBIAS output leakage currentOE = 1, VBIAS_RAIL = 28.5V110µA
IOLKVOFFSET output leakage currentOE = 1, VOFFSET_RAIL = 10.25V110µA
OUTPUT MICROMIRROR CLOCKING PULSE CONTROLS
tSPWSTROBE pulse width10ns
tSPSTROBE period20ns
tOHZOutput time to high impedanceOE Pin = High100ns
tOENOutput enable time from high impedanceOE Pin = Low100ns
tSUSSet-up timeFrom A[3:0], MODE[1:0], and SEL[1:0] to STROBE edge8ns
tHOSHold timeFrom A[3:0], MODE[1:0], and SEL[1:0] to STROBE edge8ns
tPBRPropagation timeFrom STROBE to VBIAS/VRESET edge 50% point.80200ns
tPROFrom STROBE to VRESET/VOFFSET edge 50% point.80200ns
tPOBFrom STROBE to VOFFSET/VBIAS edge 50% point.80200ns
tDELEdge-to-edge propagation deltaMaximum difference between the slowest and fastest propagation times for any given reset output.40ns
tCHCHOutput channel-to-channel propagation deltaMaximum difference between the slowest and fastest propagation times for any two outputs for any given edge.20ns
See Figure 7-1
There is no minimum speed for the serial port. It can be written to statically for diagnostic purposes.
GUID-06170500-6DA5-46C4-83FF-193CD2F394AE-low.gifFigure 7-1 Serial Interface Timing