DLPS227A Data sheet

DLPS227A october 2021 – june 2023 DLPA300

PRODUCTION DATA

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

PFP|80

Thermal pad, mechanical data (Package|Pins)

Orderable Information

dlps227a_oa

6.10 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SERIAL COMMUNICATION PORT INTERFACE
A⁽¹⁾	Setup SCPEN low to SCPCK	Reference to rising edge of SCPCK	360			ns
B⁽¹⁾	Byte to byte delay	Nominally 1 SCPCK cycle, rising edge to rising edge	1.9			µs
C⁽¹⁾	Setup SCPDI to SCPEN high	Last byte to secondary disable	360			ns
D⁽¹⁾	SCPCK frequency⁽²⁾		0		526	kHz
D⁽¹⁾	SCPCK period		1.9	2		µs
E⁽¹⁾	SCPCK high or low time		300			ns
F⁽¹⁾	SCPDI set-up time	Reference to falling edge of SCPCK	300			ns
G⁽¹⁾	SCPDI hold time	Reference from falling edge of SCPCK	300			ns
H⁽¹⁾	SCPDO propagation delay	Reference from rising edge of SCPCK			300	ns
	SCPEN, SCPCK, SCPDI, RESET filter (pulse reject)		150			ns
OUTPUT MICROMIRROR CLOCKING PULSES
F_PREP	Phased reset repetition frequency each output pin (non-overlapping)				50	kHz
F_GREP	Global reset repetition frequency all output pins				50	kHz
I_RLK	V_RESET output leakage current	OE = 1, VRESET_RAIL = -28.5V		-1	-10	µA
I_BLK	V_BIAS output leakage current	OE = 1, VBIAS_RAIL = 28.5V		1	10	µA
I_OLK	V_OFFSET output leakage current	OE = 1, VOFFSET_RAIL = 10.25V		1	10	µA
OUTPUT MICROMIRROR CLOCKING PULSE CONTROLS
t_SPW	STROBE pulse width		10			ns
t_SP	STROBE period		20			ns
t_OHZ	Output time to high impedance	OE Pin = High			100	ns
t_OEN	Output enable time from high impedance	OE Pin = Low			100	ns
t_SUS	Set-up time	From A[3:0], MODE[1:0], and SEL[1:0] to STROBE edge	8			ns
t_HOS	Hold time	From A[3:0], MODE[1:0], and SEL[1:0] to STROBE edge	8			ns
t_PBR	Propagation time	From STROBE to V_BIAS/V_RESET edge 50% point.	80		200	ns
t_PRO		From STROBE to V_RESET/V_OFFSET edge 50% point.	80		200	ns
t_POB		From STROBE to V_OFFSET/V_BIAS edge 50% point.	80		200	ns
t_DEL	Edge-to-edge propagation delta	Maximum difference between the slowest and fastest propagation times for any given reset output.			40	ns
t_CHCH	Output channel-to-channel propagation delta	Maximum difference between the slowest and fastest propagation times for any two outputs for any given edge.			20	ns

(1) See Figure 6-1

(2) There is no minimum speed for the serial port. It can be written to statically for diagnostic purposes.

Figure 6-1 Serial Interface Timing