DLPS052 October 2015 DLPA3000
PRODUCTION DATA.
The DMD block is continuously monitored for failures to prevent damage to the DLPA3000 and/or the DMD. Several possible failures are monitored such that the DMD voltages can be guaranteed. Failures could be, for instance, a broken control loop or a too-high or too-low converter output voltage. The overall DMD fault bit is in register 0x0C, DMD_FAULT. If any of the failures in Table 2 occur, the DMD_FAULT bit will be set high.
POWER GOOD (REGISTER 0x29) | ||
BLOCK | REGISTER BIT | THRESHOLD |
HV Regulator | DMD_PG_FAULT | DMD_RESET: 90%,
DMD_OFFSET and DMD_VBIAS: 86% rising, 66% falling |
PWR1 | BUCK_DMD1_PG_FAULT | Ratio: 72% |
PWR2 | BUCK_DMD2_PG_FAULT | Ratio: 72% |
PWR3 (LDO_2) | LDO_GP2_PG_FAULT / LDO_DMD1_PG_ FAULT | 80% rising, 60% falling |
PWR4 (LDO_1) | LDO_GP1_PG_FAULT / LDO_DMD1_PG_ FAULT | 80% rising, 60% falling |
OVER-VOLTAGE (REGISTER 0x2A) | ||
BLOCK | REGISTER BIT | THRESHOLD(V) |
PWR1 | BUCK_DMD1_OV_FAULT | Ratio: 120% |
PWR2 | BUCK_DMD2_OV_FAULT | Ratio: 120% |
PWR3 (LDO_2) | LDO_GP2_OV_FAULT / LDO_DMD1_OV_FAULT | 7 |
PWR4 (LDO_1) | LDO_GP1_OV_FAULT / LDO_DMD1_OV_FAULT | 7 |